fpga2pc.tan.qmsg

来自「我买的红色飓风FPGA,EP1C6开发板的配套USBA实验例程 use输入模块的」· QMSG 代码 · 共 11 行 · 第 1/3 页

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clkin " "Info: Detected ripple clock \"clkin\" as buffer" {  } { { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 32 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkin" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register fifo_data\[1\]~reg0 fifo_data\[7\]~reg0 275.03 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 275.03 MHz between source register \"fifo_data\[1\]~reg0\" and destination register \"fifo_data\[7\]~reg0\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.266 ns + Longest register register " "Info: + Longest register to register delay is 2.266 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fifo_data\[1\]~reg0 1 REG LC_X2_Y9_N1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y9_N1; Fanout = 4; REG Node = 'fifo_data\[1\]~reg0'" {  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "" { fifo_data[1]~reg0 } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 74 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.529 ns) + CELL(0.564 ns) 1.093 ns fifo_data\[1\]~97 2 COMB LC_X2_Y9_N1 2 " "Info: 2: + IC(0.529 ns) + CELL(0.564 ns) = 1.093 ns; Loc. = LC_X2_Y9_N1; Fanout = 2; COMB Node = 'fifo_data\[1\]~97'" {  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "1.093 ns" { fifo_data[1]~reg0 fifo_data[1]~97 } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.171 ns fifo_data\[2\]~101 3 COMB LC_X2_Y9_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.171 ns; Loc. = LC_X2_Y9_N2; Fanout = 2; COMB Node = 'fifo_data\[2\]~101'" {  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "0.078 ns" { fifo_data[1]~97 fifo_data[2]~101 } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.249 ns fifo_data\[3\]~105 4 COMB LC_X2_Y9_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.249 ns; Loc. = LC_X2_Y9_N3; Fanout = 2; COMB Node = 'fifo_data\[3\]~105'" {  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "0.078 ns" { fifo_data[2]~101 fifo_data[3]~105 } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 1.427 ns fifo_data\[4\]~109 5 COMB LC_X2_Y9_N4 3 " "Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 1.427 ns; Loc. = LC_X2_Y9_N4; Fanout = 3; COMB Node = 'fifo_data\[4\]~109'" {  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "0.178 ns" { fifo_data[3]~105 fifo_data[4]~109 } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 2.266 ns fifo_data\[7\]~reg0 6 REG LC_X2_Y9_N7 2 " "Info: 6: + IC(0.000 ns) + CELL(0.839 ns) = 2.266 ns; Loc. = LC_X2_Y9_N7; Fanout = 2; REG Node = 'fifo_data\[7\]~reg0'" {  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "0.839 ns" { fifo_data[4]~109 fifo_data[7]~reg0 } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 74 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.737 ns 76.65 % " "Info: Total cell delay = 1.737 ns ( 76.65 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.529 ns 23.35 % " "Info: Total interconnect delay = 0.529 ns ( 23.35 % )" {  } {  } 0}  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "2.266 ns" { fifo_data[1]~reg0 fifo_data[1]~97 fifo_data[2]~101 fifo_data[3]~105 fifo_data[4]~109 fifo_data[7]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.266 ns" { fifo_data[1]~reg0 fifo_data[1]~97 fifo_data[2]~101 fifo_data[3]~105 fifo_data[4]~109 fifo_data[7]~reg0 } { 0.000ns 0.529ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.564ns 0.078ns 0.078ns 0.178ns 0.839ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 9.191 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 9.191 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "" { clk } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.587 ns) + CELL(0.935 ns) 3.991 ns clkin 2 REG LC_X19_Y10_N2 13 " "Info: 2: + IC(1.587 ns) + CELL(0.935 ns) = 3.991 ns; Loc. = LC_X19_Y10_N2; Fanout = 13; REG Node = 'clkin'" {  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "2.522 ns" { clk clkin } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 32 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.489 ns) + CELL(0.711 ns) 9.191 ns fifo_data\[7\]~reg0 3 REG LC_X2_Y9_N7 2 " "Info: 3: + IC(4.489 ns) + CELL(0.711 ns) = 9.191 ns; Loc. = LC_X2_Y9_N7; Fanout = 2; REG Node = 'fifo_data\[7\]~reg0'" {  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "5.200 ns" { clkin fifo_data[7]~reg0 } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 74 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 33.89 % " "Info: Total cell delay = 3.115 ns ( 33.89 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.076 ns 66.11 % " "Info: Total interconnect delay = 6.076 ns ( 66.11 % )" {  } {  } 0}  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "9.191 ns" { clk clkin fifo_data[7]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.191 ns" { clk clk~out0 clkin fifo_data[7]~reg0 } { 0.000ns 0.000ns 1.587ns 4.489ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 9.191 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 9.191 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "" { clk } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.587 ns) + CELL(0.935 ns) 3.991 ns clkin 2 REG LC_X19_Y10_N2 13 " "Info: 2: + IC(1.587 ns) + CELL(0.935 ns) = 3.991 ns; Loc. = LC_X19_Y10_N2; Fanout = 13; REG Node = 'clkin'" {  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "2.522 ns" { clk clkin } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 32 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.489 ns) + CELL(0.711 ns) 9.191 ns fifo_data\[1\]~reg0 3 REG LC_X2_Y9_N1 4 " "Info: 3: + IC(4.489 ns) + CELL(0.711 ns) = 9.191 ns; Loc. = LC_X2_Y9_N1; Fanout = 4; REG Node = 'fifo_data\[1\]~reg0'" {  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "5.200 ns" { clkin fifo_data[1]~reg0 } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 74 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 33.89 % " "Info: Total cell delay = 3.115 ns ( 33.89 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.076 ns 66.11 % " "Info: Total interconnect delay = 6.076 ns ( 66.11 % )" {  } {  } 0}  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "9.191 ns" { clk clkin fifo_data[1]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.191 ns" { clk clk~out0 clkin fifo_data[1]~reg0 } { 0.000ns 0.000ns 1.587ns 4.489ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0}  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "9.191 ns" { clk clkin fifo_data[7]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.191 ns" { clk clk~out0 clkin fifo_data[7]~reg0 } { 0.000ns 0.000ns 1.587ns 4.489ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "9.191 ns" { clk clkin fifo_data[1]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.191 ns" { clk clk~out0 clkin fifo_data[1]~reg0 } { 0.000ns 0.000ns 1.587ns 4.489ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 74 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 74 -1 0 } }  } 0}  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "2.266 ns" { fifo_data[1]~reg0 fifo_data[1]~97 fifo_data[2]~101 fifo_data[3]~105 fifo_data[4]~109 fifo_data[7]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.266 ns" { fifo_data[1]~reg0 fifo_data[1]~97 fifo_data[2]~101 fifo_data[3]~105 fifo_data[4]~109 fifo_data[7]~reg0 } { 0.000ns 0.529ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.564ns 0.078ns 0.078ns 0.178ns 0.839ns } } } { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "9.191 ns" { clk clkin fifo_data[7]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.191 ns" { clk clk~out0 clkin fifo_data[7]~reg0 } { 0.000ns 0.000ns 1.587ns 4.489ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "9.191 ns" { clk clkin fifo_data[1]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.191 ns" { clk clk~out0 clkin fifo_data[1]~reg0 } { 0.000ns 0.000ns 1.587ns 4.489ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0}  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "" { fifo_data[7]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { fifo_data[7]~reg0 } {  } {  } } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 74 -1 0 } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "fifo_data\[0\]~reg0 fifo_full clk 0.028 ns register " "Info: tsu for register \"fifo_data\[0\]~reg0\" (data pin = \"fifo_full\", clock pin = \"clk\") is 0.028 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.182 ns + Longest pin register " "Info: + Longest pin to register delay is 9.182 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns fifo_full 1 PIN PIN_54 3 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_54; Fanout = 3; PIN Node = 'fifo_full'" {  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "" { fifo_full } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.789 ns) + CELL(0.590 ns) 7.848 ns fifo_data\[7\]~8 2 COMB LC_X2_Y9_N9 8 " "Info: 2: + IC(5.789 ns) + CELL(0.590 ns) = 7.848 ns; Loc. = LC_X2_Y9_N9; Fanout = 8; COMB Node = 'fifo_data\[7\]~8'" {  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "6.379 ns" { fifo_full fifo_data[7]~8 } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.467 ns) + CELL(0.867 ns) 9.182 ns fifo_data\[0\]~reg0 3 REG LC_X2_Y9_N0 4 " "Info: 3: + IC(0.467 ns) + CELL(0.867 ns) = 9.182 ns; Loc. = LC_X2_Y9_N0; Fanout = 4; REG Node = 'fifo_data\[0\]~reg0'" {  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "1.334 ns" { fifo_data[7]~8 fifo_data[0]~reg0 } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 74 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.926 ns 31.87 % " "Info: Total cell delay = 2.926 ns ( 31.87 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.256 ns 68.13 % " "Info: Total interconnect delay = 6.256 ns ( 68.13 % )" {  } {  } 0}  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "9.182 ns" { fifo_full fifo_data[7]~8 fifo_data[0]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.182 ns" { fifo_full fifo_full~out0 fifo_data[7]~8 fifo_data[0]~reg0 } { 0.000ns 0.000ns 5.789ns 0.467ns } { 0.000ns 1.469ns 0.590ns 0.867ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 74 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 9.191 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 9.191 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "" { clk } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.587 ns) + CELL(0.935 ns) 3.991 ns clkin 2 REG LC_X19_Y10_N2 13 " "Info: 2: + IC(1.587 ns) + CELL(0.935 ns) = 3.991 ns; Loc. = LC_X19_Y10_N2; Fanout = 13; REG Node = 'clkin'" {  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "2.522 ns" { clk clkin } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 32 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.489 ns) + CELL(0.711 ns) 9.191 ns fifo_data\[0\]~reg0 3 REG LC_X2_Y9_N0 4 " "Info: 3: + IC(4.489 ns) + CELL(0.711 ns) = 9.191 ns; Loc. = LC_X2_Y9_N0; Fanout = 4; REG Node = 'fifo_data\[0\]~reg0'" {  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "5.200 ns" { clkin fifo_data[0]~reg0 } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 74 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 33.89 % " "Info: Total cell delay = 3.115 ns ( 33.89 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.076 ns 66.11 % " "Info: Total interconnect delay = 6.076 ns ( 66.11 % )" {  } {  } 0}  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "9.191 ns" { clk clkin fifo_data[0]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.191 ns" { clk clk~out0 clkin fifo_data[0]~reg0 } { 0.000ns 0.000ns 1.587ns 4.489ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0}  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "9.182 ns" { fifo_full fifo_data[7]~8 fifo_data[0]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.182 ns" { fifo_full fifo_full~out0 fifo_data[7]~8 fifo_data[0]~reg0 } { 0.000ns 0.000ns 5.789ns 0.467ns } { 0.000ns 1.469ns 0.590ns 0.867ns } } } { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "9.191 ns" { clk clkin fifo_data[0]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.191 ns" { clk clk~out0 clkin fifo_data[0]~reg0 } { 0.000ns 0.000ns 1.587ns 4.489ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk fifo_data\[7\] fifo_data\[7\]~reg0 14.078 ns register " "Info: tco from clock \"clk\" to destination pin \"fifo_data\[7\]\" through register \"fifo_data\[7\]~reg0\" is 14.078 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 9.191 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 9.191 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "" { clk } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.587 ns) + CELL(0.935 ns) 3.991 ns clkin 2 REG LC_X19_Y10_N2 13 " "Info: 2: + IC(1.587 ns) + CELL(0.935 ns) = 3.991 ns; Loc. = LC_X19_Y10_N2; Fanout = 13; REG Node = 'clkin'" {  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "2.522 ns" { clk clkin } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 32 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.489 ns) + CELL(0.711 ns) 9.191 ns fifo_data\[7\]~reg0 3 REG LC_X2_Y9_N7 2 " "Info: 3: + IC(4.489 ns) + CELL(0.711 ns) = 9.191 ns; Loc. = LC_X2_Y9_N7; Fanout = 2; REG Node = 'fifo_data\[7\]~reg0'" {  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "5.200 ns" { clkin fifo_data[7]~reg0 } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 74 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 33.89 % " "Info: Total cell delay = 3.115 ns ( 33.89 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.076 ns 66.11 % " "Info: Total interconnect delay = 6.076 ns ( 66.11 % )" {  } {  } 0}  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "9.191 ns" { clk clkin fifo_data[7]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.191 ns" { clk clk~out0 clkin fifo_data[7]~reg0 } { 0.000ns 0.000ns 1.587ns 4.489ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 74 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.663 ns + Longest register pin " "Info: + Longest register to pin delay is 4.663 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fifo_data\[7\]~reg0 1 REG LC_X2_Y9_N7 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y9_N7; Fanout = 2; REG Node = 'fifo_data\[7\]~reg0'" {  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "" { fifo_data[7]~reg0 } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 74 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.555 ns) + CELL(2.108 ns) 4.663 ns fifo_data\[7\] 2 PIN PIN_65 0 " "Info: 2: + IC(2.555 ns) + CELL(2.108 ns) = 4.663 ns; Loc. = PIN_65; Fanout = 0; PIN Node = 'fifo_data\[7\]'" {  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "4.663 ns" { fifo_data[7]~reg0 fifo_data[7] } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns 45.21 % " "Info: Total cell delay = 2.108 ns ( 45.21 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.555 ns 54.79 % " "Info: Total interconnect delay = 2.555 ns ( 54.79 % )" {  } {  } 0}  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "4.663 ns" { fifo_data[7]~reg0 fifo_data[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.663 ns" { fifo_data[7]~reg0 fifo_data[7] } { 0.000ns 2.555ns } { 0.000ns 2.108ns } } }  } 0}  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "9.191 ns" { clk clkin fifo_data[7]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.191 ns" { clk clk~out0 clkin fifo_data[7]~reg0 } { 0.000ns 0.000ns 1.587ns 4.489ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "4.663 ns" { fifo_data[7]~reg0 fifo_data[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.663 ns" { fifo_data[7]~reg0 fifo_data[7] } { 0.000ns 2.555ns } { 0.000ns 2.108ns } } }  } 0}