fpga2pc.map.qmsg

我买的红色飓风FPGA,EP1C6开发板的配套USBA实验例程 use输入模块的程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 23 15:01:13 2006 " "Info: Processing started: Thu Feb 23 15:01:13 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off USB_IN -c fpga2pc " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off USB_IN -c fpga2pc" {  } {  } 0}
{ "Warning" "WVRFX_VERI_IGNORED_ANONYMOUS_PORT" "fpga2pc fpga2pc.v(11) " "Warning: Verilog Module Declaration warning at fpga2pc.v(11): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module \"fpga2pc\"" {  } { { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 11 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../Src/fpga2pc.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../Src/fpga2pc.v" { { "Info" "ISGN_ENTITY_NAME" "1 fpga2pc " "Info: Found entity 1: fpga2pc" {  } { { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "fpga2pc " "Info: Elaborating entity \"fpga2pc\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 fpga2pc.v(44) " "Warning: Verilog HDL assignment warning at fpga2pc.v(44): truncated value with size 32 to match size of target (1)" {  } { { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 44 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "fifo_full fpga2pc.v(56) " "Warning: Verilog HDL Always Construct warning at fpga2pc.v(56): variable \"fifo_full\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 56 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 fpga2pc.v(83) " "Warning: Verilog HDL assignment warning at fpga2pc.v(83): truncated value with size 32 to match size of target (1)" {  } { { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 83 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 fpga2pc.v(84) " "Warning: Verilog HDL assignment warning at fpga2pc.v(84): truncated value with size 32 to match size of target (1)" {  } { { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 84 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 fpga2pc.v(88) " "Warning: Verilog HDL assignment warning at fpga2pc.v(88): truncated value with size 32 to match size of target (8)" {  } { { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 88 0 0 } }  } 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "fifo_rd~reg0 High " "Info: Power-up level of register \"fifo_rd~reg0\" is not specified -- using power-up level of High to minimize register" {  } { { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 19 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "fifo_rd~reg0 data_in VCC " "Warning: Reduced register \"fifo_rd~reg0\" with stuck data_in port to stuck value VCC" {  } { { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 19 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|fpga2pc\|STATE 3 0 " "Info: State machine \"\|fpga2pc\|STATE\" contains 3 states and 0 state bits" {  } { { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 33 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|fpga2pc\|STATE " "Info: Selected Auto state machine encoding method for state machine \"\|fpga2pc\|STATE\"" {  } { { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 33 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|fpga2pc\|STATE " "Info: Encoding result for state machine \"\|fpga2pc\|STATE\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "3 " "Info: Completed encoding using 3 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "STATE.IDLE " "Info: Encoded state bit \"STATE.IDLE\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "STATE.WRITE_2 " "Info: Encoded state bit \"STATE.WRITE_2\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "STATE.WRITE_1 " "Info: Encoded state bit \"STATE.WRITE_1\"" {  } { { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 33 -1 0 } }  } 0}  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|fpga2pc\|STATE.IDLE 000 " "Info: State \"\|fpga2pc\|STATE.IDLE\" uses code string \"000\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|fpga2pc\|STATE.WRITE_2 110 " "Info: State \"\|fpga2pc\|STATE.WRITE_2\" uses code string \"110\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|fpga2pc\|STATE.WRITE_1 101 " "Info: State \"\|fpga2pc\|STATE.WRITE_1\" uses code string \"101\"" {  } { { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 33 -1 0 } }  } 0}  } { { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 33 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "fifo_rd VCC " "Warning: Pin \"fifo_rd\" stuck at VCC" {  } { { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 19 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 18 -1 0 } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 32 -1 0 } }  } 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "2 " "Warning: Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "fifo_pf " "Warning: No output dependent on input pin \"fifo_pf\"" {  } { { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 15 -1 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "fifo_empty " "Warning: No output dependent on input pin \"fifo_empty\"" {  } { { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 15 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "29 " "Info: Implemented 29 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "10 " "Info: Implemented 10 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "14 " "Info: Implemented 14 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 23 15:01:14 2006 " "Info: Processing ended: Thu Feb 23 15:01:14 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}