📄 serial interface (rs-232) 4.rs-232 receiver module.mht
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Date: Wed, 19 Apr 2006 00:29:31 +0800
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<H4>RS-232 receiver module</H4>Here's what we are trying to=20
build:<BR><BR><IMG=20
=
src=3D"http://www.fpga4fun.com/images/SerialRxDmodule.gif"><BR><BR>Our=20
implementation works like that:=20
<UL>
<LI>The module assembles data from the RxD line as it comes=20
<LI>As a byte is being received, it appears on the "data" bus. =
Once a=20
complete byte has been received, "data_ready" is asserted for =
one clock=20
</LI></UL>Note that "data" is valid only when "data_ready" is =
asserted.=20
The rest of the time, don't use it as new data may come that =
shuffles it.=20
<H4>Oversampling</H4>An asynchronous receiver has to somehow get =
in-sync=20
with the incoming signal (it doesn't have access to the clock used =
during=20
transmission).=20
<UL>
<LI>To determine when a new data is coming ("start" bit), we =
oversample=20
the signal at a multiple of the baud rate frequency.=20
<LI>Once the "start" bit is detected, we sample the line at the =
known=20
baud rate to acquire the data bits. </LI></UL>Receivers =
typically=20
oversample the incoming signal at 16 times the baud rate. Here we =
use 8=20
times. At 115200 bauds, that gives a sampling rate of=20
921600Hz.<BR><BR>Let's assume that we have a "Baud8Tick" signal =
available,=20
asserted 921600 times a second.=20
<H4>The design</H4>First, the incoming "RxD" signal has no =
relationship=20
with our clock.<BR>We use two D-flipflops to oversample it, and=20
synchronize it to our clock.=20
<TABLE cellPadding=3D10>
<TBODY>
<TR>
<TD bgColor=3D#d0d0f0><B>reg</B> [1:0] =
RxD_sync;<BR><B>always</B>=20
@(<B>posedge</B> clk) <B>if</B>(Baud8Tick) RxD_sync <=3D=20
{RxD_sync[0], RxD}; </TD></TR></TBODY></TABLE><BR>We filter =
the data, so=20
that short spikes on the RxD line aren't mistaken with start bits. =
<TABLE cellPadding=3D10>
<TBODY>
<TR>
<TD bgColor=3D#d0d0f0><B>reg</B> [1:0] RxD_cnt;<BR><B>reg</B>=20
RxD_bit;<BR><BR><B>always</B> @(<B>posedge</B>=20
clk)<BR><B>if</B>(Baud8Tick)<BR><B>begin</B><BR> =20
<B>if</B>(RxD_sync[1] && RxD_cnt!=3D2'b11) RxD_cnt =
<=3D=20
RxD_cnt + 1;<BR> <B>else</B> <BR> =
<B>if</B>(~RxD_sync[1]=20
&& RxD_cnt!=3D2'b00) RxD_cnt <=3D RxD_cnt - =
1;<BR><BR> =20
<B>if</B>(RxD_cnt=3D=3D2'b00) RxD_bit <=3D 0;<BR> =20
<B>else</B><BR> <B>if</B>(RxD_cnt=3D=3D2'b11) RxD_bit =
<=3D=20
1;<BR><B>end</B> </TD></TR></TBODY></TABLE><BR>A state =
machine allows us=20
to go through each bit received, once a "start" is detected.=20
<TABLE cellPadding=3D10>
<TBODY>
<TR>
<TD bgColor=3D#d0d0f0><B>reg</B> [3:0] =
state;<BR><BR><B>always</B>=20
@(<B>posedge</B>=20
clk)<BR><B>if</B>(Baud8Tick)<BR><B>case</B>(state)<BR> =
4'b0000: <B>if</B>(~RxD_bit) state <=3D 4'b1000; // start =
bit=20
found?<BR> 4'b1000: <B>if</B>(next_bit) state <=3D =
4'b1001;=20
// bit 0<BR> 4'b1001: <B>if</B>(next_bit) state =
<=3D 4'b1010;=20
// bit 1<BR> 4'b1010: <B>if</B>(next_bit) state =
<=3D 4'b1011;=20
// bit 2<BR> 4'b1011: <B>if</B>(next_bit) state =
<=3D 4'b1100;=20
// bit 3<BR> 4'b1100: <B>if</B>(next_bit) state =
<=3D 4'b1101;=20
// bit 4<BR> 4'b1101: <B>if</B>(next_bit) state =
<=3D 4'b1110;=20
// bit 5<BR> 4'b1110: <B>if</B>(next_bit) state =
<=3D 4'b1111;=20
// bit 6<BR> 4'b1111: <B>if</B>(next_bit) state =
<=3D 4'b0001;=20
// bit 7<BR> 4'b0001: <B>if</B>(next_bit) state =
<=3D 4'b0000;=20
// stop bit<BR> default: state <=3D=20
4'b0000;<BR><B>endcase</B> =
</TD></TR></TBODY></TABLE><BR>Notice that we=20
used a "next_bit" signal, to go from bit to bit.=20
<TABLE cellPadding=3D10>
<TBODY>
<TR>
<TD bgColor=3D#d0d0f0><B>reg</B> [2:0]=20
bit_spacing;<BR><BR><B>always</B> @(<B>posedge</B>=20
clk)<BR><B>if</B>(state=3D=3D0)<BR> bit_spacing =
<=3D=20
0;<BR><B>else</B><BR><B>if</B>(Baud8Tick)<BR> =
bit_spacing=20
<=3D bit_spacing + 1;<BR><BR><B>wire</B> next_bit =3D=20
(bit_spacing=3D=3D7); </TD></TR></TBODY></TABLE><BR>Finally =
a shift register=20
collects the data bits as they come.=20
<TABLE cellPadding=3D10>
<TBODY>
<TR>
<TD bgColor=3D#d0d0f0><B>reg</B> [7:0] =
RxD_data;<BR><B>always</B>=20
@(<B>posedge</B> clk) <B>if</B>(Baud8Tick && =
next_bit=20
&& state[3]) RxD_data <=3D {RxD_bit, =
RxD_data[7:1]};=20
</TD></TR></TBODY></TABLE><BR>That's it! The complete code can =
be found <A=20
href=3D"http://www.fpga4fun.com/files/async.zip">here</A>.<BR>It =
has a few=20
improvements; follow the comments in the code.=20
<H4>Links</H4>
<UL>
<LI>More details on <A=20
=
href=3D"http://www.erg.abdn.ac.uk/users/gorry/course/phy-pages/async.html=
">Asynchronous=20
Communication</A> </LI></UL><BR><BR><A=20
href=3D"http://www.fpga4fun.com/SerialInterface5.html"><FONT =
color=3Dblue=20
size=3D2>>>> NEXT: How to use the Transmitter and =
Receiver modules=20
>>></FONT></A><BR><BR><BR>
<HR>
This page was last updated on April 07=20
2005.<BR><BR></TD></TR></TBODY></TABLE></BODY></HTML>
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