📄 serial interface (rs-232) 5.how to use the modules.mht

📁 用FPGA实现RS232通信,此代码是用VHDL语言编写
💻 MHT
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Subject: FPGAs are fun!
Date: Wed, 19 Apr 2006 00:30:04 +0800
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      </B></FONT><BR><BR></TD>
    <TD vAlign=3Dtop>
      <H4>How to use the Transmitter and Receiver modules </H4>Consider =
the=20
      following design.<BR>It does two things:=20
      <OL>
        <LI>It creates an 8-bits general purpose ("GP") output port, =
controlled=20
        by any character received on the serial port.=20
        <LI>It creates an 8-bits general purpose input port. The state =
of the=20
        port is sent back to the PC every time a character is received.=20
      </LI></OL>The GP outputs can be used to control anything remotely =
from=20
      your PC, might be LEDs on your FPGA board, or a coffee machine =
with the=20
      help of a relay.<BR><BR>
      <TABLE cellPadding=3D10>
        <TBODY>
        <TR>
          <TD bgColor=3D#d0d0f0><B>module</B> serialfun(clk, RxD, TxD, =
GPout,=20
            GPin);<BR><B>input</B> clk;<BR><B>input</B> =
RxD;<BR><B>output</B>=20
            TxD;<BR><B>output</B> [7:0] GPout;<BR><B>input</B> [7:0]=20
            GPin;<BR><BR><B>wire</B> RxD_data_ready;<BR><B>wire</B> =
[7:0]=20
            RxD_data;<BR><B>async_receiver</B> deserializer(.clk(clk),=20
            .RxD(RxD), .RxD_data_ready(RxD_data_ready),=20
            .RxD_data(RxD_data));<BR><BR><B>reg</B> [7:0]=20
            GPout;<BR><B>always</B> @(<B>posedge</B> clk)=20
            <B>if</B>(RxD_data_ready) GPout &lt;=3D=20
            =
RxD_data;<BR><BR>///////////////////////////////////////////////////<BR><=
B>reg</B>=20
            [7:0] GPin_reg;<BR><B>wire</B> TxD_busy;<BR><B>always</B>=20
            @(<B>posedge</B> clk) <B>if</B>(RxD_data_ready &amp; =
~TxD_busy)=20
            GPin_reg &lt;=3D GPin;<BR><BR><B>async_transmitter</B>=20
            serializer(.clk(clk), .TxD(TxD), .TxD_start(RxD_data_ready =
&amp;=20
            ~TxD_busy), .TxD_data(GPin_reg),=20
            .TxD_busy(TxD_busy));<BR><BR><B>endmodule</B>=20
      </TD></TR></TBODY></TABLE><BR>Remember to grab the async_receiver =
and=20
      async_transmitter modules <A=20
      href=3D"http://www.fpga4fun.com/files/async.zip">here</A>, and to =
update the=20
      clock values inside.<BR><BR>Have fun! <BR><BR><BR><BR>
      <HR>
      This page was last updated on April 07=20
2005.<BR><BR></TD></TR></TBODY></TABLE></BODY></HTML>
💿 文件大小 48 K
👤 上传用户 bonylee_java
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#FPGA #VHDL #232 #RS
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