📄 serial interface (rs-232) 3.rs-232 transimitter module.mht
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Date: Wed, 19 Apr 2006 00:28:59 +0800
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<H4>RS-232 transmitter module</H4>Here's what we are trying to=20
build:<BR><BR><IMG=20
=
src=3D"http://www.fpga4fun.com/images/SerialTxDmodule.gif"><BR><BR>It =
works=20
like that:=20
<UL>
<LI>The transmitter takes an 8-bits data, and serializes it =
(starting=20
when the "TxD_start" signal is asserted).=20
<LI>The "busy" signal is asserted while a transmission occurs. =
The=20
"TxD_start" signal is ignored during that time. </LI></UL>The =
RS-232=20
parameters used are fixed: 8-bits data, 2 stop bits, no-parity.=20
<H4>Serializing the data</H4>We assume that we have a "BaudTick" =
signal=20
available, asserted 115200 times a second.<BR><BR>We need to =
generate the=20
start bit, the 8 data bits, and the stop bits.<BR>A state machine =
seems=20
appropriate.<BR><BR>
<TABLE cellPadding=3D10>
<TBODY>
<TR>
<TD bgColor=3D#d0d0f0><B>reg</B> [3:0] =
state;<BR><BR><B>always</B>=20
@(<B>posedge</B> clk)<BR><B>case</B>(state)<BR> =
4'b0000:=20
<B>if</B>(TxD_start) state <=3D 4'b0100;<BR> =
4'b0100:=20
<B>if</B>(BaudTick) state <=3D 4'b1000; // =
start<BR> 4'b1000:=20
<B>if</B>(BaudTick) state <=3D 4'b1001; // bit =
0<BR> 4'b1001:=20
<B>if</B>(BaudTick) state <=3D 4'b1010; // bit =
1<BR> 4'b1010:=20
<B>if</B>(BaudTick) state <=3D 4'b1011; // bit =
2<BR> 4'b1011:=20
<B>if</B>(BaudTick) state <=3D 4'b1100; // bit =
3<BR> 4'b1100:=20
<B>if</B>(BaudTick) state <=3D 4'b1101; // bit =
4<BR> 4'b1101:=20
<B>if</B>(BaudTick) state <=3D 4'b1110; // bit =
5<BR> 4'b1110:=20
<B>if</B>(BaudTick) state <=3D 4'b1111; // bit =
6<BR> 4'b1111:=20
<B>if</B>(BaudTick) state <=3D 4'b0001; // bit =
7<BR> 4'b0001:=20
<B>if</B>(BaudTick) state <=3D 4'b0010; // =
stop1<BR> 4'b0010:=20
<B>if</B>(BaudTick) state <=3D 4'b0000; // =
stop2<BR> default:=20
<B>if</B>(BaudTick) state <=3D 4'b0000;<BR><B>endcase</B> =
</TD></TR></TBODY></TABLE><BR>Notice how the state machine =
starts right=20
when "TxD_start" is asserted, but then only advances when =
"BaudTick" is=20
asserted.<BR><BR>Now, we just need to generate the "TxD" =
output.<BR>
<TABLE cellPadding=3D10>
<TBODY>
<TR>
<TD bgColor=3D#d0d0f0><B>reg</B> muxbit;<BR><BR><B>always</B>=20
@(state[2:0])<BR><B>case</B>(state[2:0])<BR> 0: muxbit =
<=3D=20
TxD_data[0];<BR> 1: muxbit <=3D =
TxD_data[1];<BR> 2:=20
muxbit <=3D TxD_data[2];<BR> 3: muxbit <=3D=20
TxD_data[3];<BR> 4: muxbit <=3D =
TxD_data[4];<BR> 5:=20
muxbit <=3D TxD_data[5];<BR> 6: muxbit <=3D=20
TxD_data[6];<BR> 7: muxbit <=3D=20
TxD_data[7];<BR><B>endcase</B><BR><BR>// combine start, =
data, and=20
stop bits together<BR><B>assign</B> TxD =3D (state<4) | =
(state[3]=20
& muxbit); </TD></TR></TBODY></TABLE><BR>Notice that the =
"TxD_data"=20
input needs to stay stable while the character is being sent. Keep =
that in=20
mind when you use this module. Otherwise feel free to improve this =
module=20
by registering internally "TxD_data" when transmission=20
starts.<BR><BR>That's it! The complete code can be found <A=20
href=3D"http://www.fpga4fun.com/files/async.zip">here</A>. =
<BR><BR><A=20
href=3D"http://www.fpga4fun.com/SerialInterface4.html"><FONT =
color=3Dblue=20
size=3D2>>>> NEXT: RS-232 receiver module=20
>>></FONT></A><BR><BR><BR>
<HR>
This page was last updated on April 07=20
2005.<BR><BR></TD></TR></TBODY></TABLE></BODY></HTML>
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