📄 serial interface (rs-232) 2.baud generator.mht
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Subject: FPGAs are fun!
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<H4>Baud generator</H4>Here we want to use the serial link at =
maximum=20
speed, i.e. 115200 bauds. Other slower speeds would also be easy =
to=20
generate.<BR><BR>FPGAs usually run at speed well above 115200Hz =
(RS-232 is=20
pretty slow by today's standards). That means we use a high-speed =
clock=20
and divide it down to generate a "tick" as close as possible to =
115200=20
times a second.=20
<H4>Synchronous tick from a 1.8432MHz clock</H4>Traditionally, =
RS-232=20
chips use a 1.8432MHz clock, because that makes generating the =
standard=20
baud frequencies very easy. So let's assume we have a 1.8432MHz =
clock=20
available.<BR><BR>1.8432MHz divided by 16 gives 115200Hz, what a=20
coincidence!<BR><BR>
<TABLE cellPadding=3D10>
<TBODY>
<TR>
<TD bgColor=3D#d0d0f0><B>reg</B> [3:0] =
BaudDivCnt;<BR><B>always</B>=20
@(<B>posedge</B> clk) BaudDivCnt <=3D BaudDivCnt +=20
1;<BR><BR><B>wire</B> BaudTick =3D (BaudDivCnt=3D=3D15);=20
</TD></TR></TBODY></TABLE><BR>So "BaudTick" is asserted once every =
16=20
clocks, i.e. 115200 times a second when using a 1.8432MHz clock.=20
<H4>Synchronous tick from any frequency</H4>The earlier generator =
was=20
assuming the use of a 1.8432MHz clock. But what do you do if all =
your have=20
is, say, a 2MHz clock? To generate 115200Hz from a 2MHz clock, you =
divide=20
the clock by "17.361111111..." Not exactly a round number. The =
solution is=20
to divide sometimes by 17, sometimes by 18, making sure the ratio =
stays=20
"17.361111111". That's actually easy to do.<BR><BR>Look at the =
following=20
"C" code:<BR>
<TABLE cellPadding=3D10>
<TBODY>
<TR>
<TD bgColor=3D#d0d0f0>while(1) // repeat =
forever<BR>{<BR> acc +=3D=20
115200;<BR> if(acc>=3D2000000) printf("*"); else =
printf("=20
");<BR><BR> acc %=3D=20
2000000;<BR>}<BR></TD></TR></TBODY></TABLE><BR>That prints the "*" =
in the=20
exact ratio, once every "17.361111111..." loops on =
average.<BR><BR>To=20
obtain the same thing efficiently in an FPGA, we rely on the fact =
that the=20
serial interface can tolerate a few % of error in the baud =
frequency=20
generator. It really won't matter if we use "17.3" or "17.4".=20
<H4>FPGA baud generator</H4>It is desirable that the 2000000 be a =
power of=20
two. Obviously 2000000 is not a power of two. So we change the =
ratio.=20
Instead of the ratio "2000000/115200", let's use "1024/59" =3D =
17.356.=20
That's very close to our ideal ratio, and makes an efficient FPGA=20
implementation.<BR><BR>
<TABLE cellPadding=3D10>
<TBODY>
<TR>
<TD bgColor=3D#d0d0f0>// 10 bits for the accumulator ([9:0]), =
and one=20
extra bit for the accumulator carry-out ([10])<BR><B>reg</B> =
[10:0]=20
acc; // 11 bits total!<BR><BR><B>always</B> =
@(<B>posedge</B>=20
clk)<BR> acc <=3D acc[9:0] + 59; // use only 10 =
bits from the=20
previous result, but save the full 11 =
bits<BR><BR><B>wire</B>=20
BaudTick =3D acc[10]; // so that the 11th bit is the =
carry-out=20
</TD></TR></TBODY></TABLE><BR>Using our 2MHz clock, "BaudTick" =
is asserted=20
115234 times a second, a 0.03% error from the ideal 115200.=20
<H4>Parameterized FPGA baud generator</H4>The previous design was =
using a=20
10 bits accumulator, but as the clock frequency increases, more =
bits are=20
required.<BR><BR>Here's a design with a 25MHz clock and a 16 bits=20
accumulator. The design is parameterized, so easy to =
customize.<BR><BR>
<TABLE cellPadding=3D10>
<TBODY>
<TR>
<TD bgColor=3D#d0d0f0><B>parameter</B> ClkFrequency =3D =
25000000; //=20
25MHz<BR><B>parameter</B> Baud =3D =
115200;<BR><B>parameter</B>=20
BaudGeneratorAccWidth =3D 16;<BR><B>parameter</B> =
BaudGeneratorInc =3D=20
=
(Baud<<BaudGeneratorAccWidth)/ClkFrequency;<BR><BR><B>reg</B>=20
[BaudGeneratorAccWidth:0] BaudGeneratorAcc;<BR><B>always</B> =
@(<B>posedge</B> clk)<BR> BaudGeneratorAcc <=3D=20
BaudGeneratorAcc[BaudGeneratorAccWidth-1:0] +=20
BaudGeneratorInc;<BR><BR><B>wire</B> BaudTick =3D=20
BaudGeneratorAcc[BaudGeneratorAccWidth]; =
</TD></TR></TBODY></TABLE><BR>One=20
last implementation issue: the "BaudGeneratorInc" calculation is =
wrong,=20
due to the fact that Verilog uses 32 bits intermediate results, =
and the=20
calculation exceeds that. Change the line as follow for a=20
workaround.<BR><BR>
<TABLE cellPadding=3D10>
<TBODY>
<TR>
<TD bgColor=3D#d0d0f0><B>parameter</B> BaudGeneratorInc =3D=20
=
((Baud<<(BaudGeneratorAccWidth-4))+(ClkFrequency>>5))/(ClkFre=
quency>>4);=20
</TD></TR></TBODY></TABLE><BR>This line has also the added =
advantage to=20
round the result instead of truncating.<BR><BR>That's it.<BR>Now =
that we=20
have a precise enough Baud generator, we can go ahead with the =
RS-232=20
transmitter and receiver modules. <BR><BR><A=20
href=3D"http://www.fpga4fun.com/SerialInterface3.html"><FONT =
color=3Dblue=20
size=3D2>>>> NEXT: RS-232 transmitter module=20
>>></FONT></A><BR><BR><BR>
<HR>
This page was last updated on December 01=20
2004.<BR><BR></TD></TR></TBODY></TABLE></BODY></HTML>
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