vga_key.tlg

利用VERILOG编写的基于XILINX的SPARTAN板的VGA接口显示程序

Selecting top level module vga_key
@N:"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\vs_hs.v":3:7:3:11|Synthesizing module vs_hs

@N:"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":3:7:3:13|Synthesizing module savecon

@N: CG179 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":127:18:127:18|Removing redundant assignment
@W: CL112 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":63:0:63:5|Feedback mux created for signal dateb. Did you forget the set/reset assignment for this signal?
@W: CL190 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Optimizing register bit y[0] to a constant 0
@W: CL190 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Optimizing register bit y[1] to a constant 0
@W: CL190 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Optimizing register bit y[2] to a constant 0
@W: CL190 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Optimizing register bit y[3] to a constant 0
@W: CL190 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Optimizing register bit y[4] to a constant 0
@W: CL190 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Optimizing register bit z[0] to a constant 0
@W: CL190 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Optimizing register bit z[1] to a constant 0
@W: CL190 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Optimizing register bit z[2] to a constant 0
@W: CL190 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Optimizing register bit z[3] to a constant 0
@W: CL190 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Optimizing register bit z[4] to a constant 0
@W: CL171 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Pruning Register bit <4> of z[14:0] 

@W: CL171 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Pruning Register bit <3> of z[14:0] 

@W: CL171 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Pruning Register bit <2> of z[14:0] 

@W: CL171 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Pruning Register bit <1> of z[14:0] 

@W: CL171 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Pruning Register bit <0> of z[14:0] 

@W: CL171 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Pruning Register bit <4> of y[14:0] 

@W: CL171 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Pruning Register bit <3> of y[14:0] 

@W: CL171 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Pruning Register bit <2> of y[14:0] 

@W: CL171 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Pruning Register bit <1> of y[14:0] 

@W: CL171 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Pruning Register bit <0> of y[14:0] 

@N:"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\save.v":40:7:40:10|Synthesizing module save

@W: CG146 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\save.v":40:7:40:10|Creating black box for empty module save

@N:"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\sendsave.v":3:7:3:14|Synthesizing module sendsave

@W: CL112 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\sendsave.v":22:0:22:5|Feedback mux created for signal wea. Did you forget the set/reset assignment for this signal?
@N:"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\vga.v":3:7:3:9|Synthesizing module vga

@W: CS148 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\vga.v":34:5:34:6|Undriven input dinb, tying to 0
@N:"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\clkdiv.v":3:7:3:12|Synthesizing module clkdiv

@N:"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\buttonte.v":3:7:3:14|Synthesizing module buttonte

@N:"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\change.v":3:7:3:12|Synthesizing module change

@N:"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\key_display.v":3:7:3:17|Synthesizing module key_display

@N:"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\vga_key.v":3:7:3:13|Synthesizing module vga_key