stdout.log

利用VERILOG编写的基于XILINX的SPARTAN板的VGA接口显示程序

License checkout: synplifypro

Starting:    d:\Program Files\Synplicity\fpga_81\bin\mbin\synplify.exe
Install:     d:\Program Files\Synplicity\fpga_81
Date:        Sat May 03 16:17:34 2008
Version:     8.1

Version 8.1

Arguments:   -pro -batch -splash -launchmode vga_key.prj -tcl vga_key_map.tcl
ProductType: synplify_pro

License: synplifypro node-locked 
Running in Xilinx Mode



Running synthesis on vga_key:VGAVGA

log file: "F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\vga_key.srr"


Running Verilog Compiler...

Verilog Compiler Completed


Verilog Compiler: 0 errors, 27 warnings, 13 notes - from log file F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\vga_key.srr


Total: 0 errors, 27 warnings, 13 notes

Running SPARTAN3E Mapper...

Launching mapper in pro mode

SPARTAN3E Mapper Completed with warnings


SPARTAN3E Mapper: 0 errors, 1 warning, 36 notes - from log file F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\vga_key.srr


Total: 0 errors, 28 warnings, 49 notes

TCL script complete: "F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\vga_key_map.tcl"

exit status=0