vga_key.srr

利用VERILOG编写的基于XILINX的SPARTAN板的VGA接口显示程序

   2		0h:0m:24s		    -3.72ns		 623 /       257
   3		0h:0m:24s		    -3.72ns		 623 /       257
Timing driven replication report
No replication required.

   4		0h:0m:24s		    -3.72ns		 623 /       257
   5		0h:0m:24s		    -3.33ns		 627 /       257
   6		0h:0m:24s		    -3.07ns		 629 /       257
   7		0h:0m:24s		    -2.94ns		 647 /       257
   8		0h:0m:25s		    -2.94ns		 648 /       257
   9		0h:0m:25s		    -2.94ns		 648 /       257
  10		0h:0m:25s		    -2.94ns		 648 /       257
------------------------------------------------------------

Timing driven replication report
@N: FX235 :"f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v":63:0:63:5|Instance "m1.m2.N_335_i" with 2 loads has been replicated 1 time(s) to improve timing 
@N: FX235 :"f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v":63:0:63:5|Instance "m1.m2.N_333_i" with 2 loads has been replicated 1 time(s) to improve timing 
@N: FX235 :"f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v":63:0:63:5|Instance "m1.m2.N_331_i" with 2 loads has been replicated 1 time(s) to improve timing 
@N: FX235 :"f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v":63:0:63:5|Instance "m1.m2.N_329_i" with 2 loads has been replicated 1 time(s) to improve timing 
@N: FX235 :"f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v":63:0:63:5|Instance "m1.m2.N_327_i" with 2 loads has been replicated 1 time(s) to improve timing 
Added 0 Registers via timing driven replication
Added 5 LUTs via timing driven replication

Timing driven replication report
@N: FX235 :"f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v":92:0:92:5|Instance "m1.m2.z[5]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX235 :"f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v":63:0:63:5|Instance "m1.m2.N_325_i" with 2 loads has been replicated 1 time(s) to improve timing 
@N: FX235 :"f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v":63:0:63:5|Instance "m1.m2.N_323_i" with 2 loads has been replicated 1 time(s) to improve timing 
Added 1 Registers via timing driven replication
Added 2 LUTs via timing driven replication

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:0m:25s		    -3.27ns		 672 /       258
   2		0h:0m:26s		    -3.18ns		 685 /       258
   3		0h:0m:26s		    -3.18ns		 685 /       258
   4		0h:0m:26s		    -3.18ns		 688 /       258
   5		0h:0m:26s		    -3.18ns		 688 /       258
Timing driven replication report
No replication required.

   6		0h:0m:26s		    -3.18ns		 688 /       258
   7		0h:0m:26s		    -3.05ns		 688 /       258
   8		0h:0m:26s		    -3.09ns		 692 /       258
   9		0h:0m:26s		    -3.09ns		 692 /       258
  10		0h:0m:26s		    -3.09ns		 692 /       258
------------------------------------------------------------

Net buffering Report for view:work.vga_key(verilog):
No nets needed buffering.

@N: FX164 |The option to pack flops in the IOB has not been specified 
Writing Analyst data base F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\vga_key.srm
Writing EDIF Netlist and constraint files
Found clock vga_key|clk with period 9.50ns 
Found clock clkdiv|count16_inferred_clock[14] with period 4.15ns 
@W: MT253 :"f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\vga.v":34:5:34:6|Blackbox save is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 


##### START OF TIMING REPORT #####[
# Timing Report written on Sat May 03 16:18:18 2008
#


Top view:               vga_key
Requested Frequency:    105.2 MHz
Wire load mode:         top
Paths requested:        0
Constraint File(s):    F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\vga_key.sdc
                       
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: -1.677

                                      Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock                        Frequency     Frequency     Period        Period        Slack      Type         Group                
-------------------------------------------------------------------------------------------------------------------------------------------
clkdiv|count16_inferred_clock[14]     241.1 MHz     204.9 MHz     4.148         4.880         -0.732     inferred     Autoconstr_clkgroup_1
vga_key|clk                           105.2 MHz     89.5 MHz      9.502         11.179        -1.677     inferred     Autoconstr_clkgroup_0
===========================================================================================================================================





Clock Relationships
*******************

Clocks                                                                |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
-------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                           Ending                             |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
-------------------------------------------------------------------------------------------------------------------------------------------------------------
clkdiv|count16_inferred_clock[14]  clkdiv|count16_inferred_clock[14]  |  4.148       -0.732  |  No paths    -      |  No paths    -      |  No paths    -    
clkdiv|count16_inferred_clock[14]  vga_key|clk                        |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
vga_key|clk                        vga_key|clk                        |  9.502       -1.677  |  No paths    -      |  No paths    -      |  No paths    -    
=============================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

		No IO constraint found 


##### END OF TIMING REPORT #####]

---------------------------------------
Resource Usage Report for vga_key 

Mapping to part: xc3s100etq144-4
Cell usage:
FDC             146 uses
FDCE            56 uses
FDE             2 uses
FDP             54 uses
GND             7 uses
MULT_AND        14 uses
MUXCY           7 uses
MUXCY_L         192 uses
MUXF5           15 uses
VCC             3 uses
XORCY           171 uses
save            1 use
LUT1            135 uses
LUT2            119 uses
LUT3            136 uses
LUT4            292 uses

I/O primitives: 27
IBUF           6 uses
OBUF           21 uses

BUFG           1 use

BUFGP          1 use

I/O Register bits:                  0
Register bits not including I/Os:   258 (9%)

Global Clock Buffers: 2 of 24 (8%)


Mapping Summary:
Total  LUTs: 682 (24%)

Mapper successful!
Process took 0h:0m:30s realtime, 0h:0m:30s cputime
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