vga_key.srr

利用VERILOG编写的基于XILINX的SPARTAN板的VGA接口显示程序

#Program: Synplify Pro 8.1
#OS: Windows_NT

$ Start of Compile
#Sat May 03 16:17:34 2008

Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May  3 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved

@I::"d:\Program Files\Synplicity\fpga_81\lib\xilinx\unisim.v"
@I::"d:\Program Files\Synplicity\fpga_81\bin\..\lib\xilinx\unisim.v"
@I::"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\vs_hs.v"
@I::"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\sendsave.v"
@I::"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v"
@I::"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\save.v"
@N:"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\save.v":66:12:66:24|Read directive translate_off 
@N:"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\save.v":127:12:127:23|Read directive translate_on 
@W: CS141 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\save.v":130:12:130:20|Unrecognized synthesis directive attribute
@W: CS141 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\save.v":131:13:131:21|Unrecognized synthesis directive attribute
@W: CS141 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\save.v":135:13:135:21|Unrecognized synthesis directive attribute
@I::"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\clkdiv.v"
@I::"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\change.v"
@I::"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\buttonte.v"
@I::"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\vga.v"
@I::"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\key_display.v"
@I::"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\vga_key.v"
Verilog syntax check successful!
File F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\vs_hs.v changed - recompiling
Selecting top level module vga_key
@N:"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\vs_hs.v":3:7:3:11|Synthesizing module vs_hs

@N:"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":3:7:3:13|Synthesizing module savecon

@N: CG179 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":127:18:127:18|Removing redundant assignment
@W: CL112 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":63:0:63:5|Feedback mux created for signal dateb. Did you forget the set/reset assignment for this signal?
@W: CL190 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Optimizing register bit y[0] to a constant 0
@W: CL190 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Optimizing register bit y[1] to a constant 0
@W: CL190 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Optimizing register bit y[2] to a constant 0
@W: CL190 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Optimizing register bit y[3] to a constant 0
@W: CL190 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Optimizing register bit y[4] to a constant 0
@W: CL190 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Optimizing register bit z[0] to a constant 0
@W: CL190 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Optimizing register bit z[1] to a constant 0
@W: CL190 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Optimizing register bit z[2] to a constant 0
@W: CL190 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Optimizing register bit z[3] to a constant 0
@W: CL190 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Optimizing register bit z[4] to a constant 0
@W: CL171 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Pruning Register bit <4> of z[14:0] 

@W: CL171 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Pruning Register bit <3> of z[14:0] 

@W: CL171 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Pruning Register bit <2> of z[14:0] 

@W: CL171 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Pruning Register bit <1> of z[14:0] 

@W: CL171 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Pruning Register bit <0> of z[14:0] 

@W: CL171 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Pruning Register bit <4> of y[14:0] 

@W: CL171 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Pruning Register bit <3> of y[14:0] 

@W: CL171 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Pruning Register bit <2> of y[14:0] 

@W: CL171 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Pruning Register bit <1> of y[14:0] 

@W: CL171 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v":92:0:92:5|Pruning Register bit <0> of y[14:0] 

@N:"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\save.v":40:7:40:10|Synthesizing module save

@W: CG146 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\save.v":40:7:40:10|Creating black box for empty module save

@N:"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\sendsave.v":3:7:3:14|Synthesizing module sendsave

@W: CL112 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\sendsave.v":22:0:22:5|Feedback mux created for signal wea. Did you forget the set/reset assignment for this signal?
@N:"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\vga.v":3:7:3:9|Synthesizing module vga

@W: CS148 :"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\vga.v":34:5:34:6|Undriven input dinb, tying to 0
@N:"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\clkdiv.v":3:7:3:12|Synthesizing module clkdiv

@N:"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\buttonte.v":3:7:3:14|Synthesizing module buttonte

@N:"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\change.v":3:7:3:12|Synthesizing module change

@N:"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\key_display.v":3:7:3:17|Synthesizing module key_display

@N:"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\vga_key.v":3:7:3:13|Synthesizing module vga_key

@END
Process took 0h:00m:07s realtime, 0h:00m:07s cputime
# Sat May 03 16:17:43 2008

###########################################################[
Version 8.1
Synplicity Xilinx Technology Mapper, Version 8.1.0, Build 540R, Built May  9 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved
Reading constraint file: F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\vga_key.sdc
Reading Xilinx I/O pad type table from file <d:\Program Files\Synplicity\fpga_81\lib/xilinx/x_io_tbl.txt> 
Reading Xilinx Rocket I/O parameter type table from file <d:\Program Files\Synplicity\fpga_81\lib/xilinx/gttype.txt> 


Automatic dissolve at startup in view:work.vga(verilog) of m4(sendsave)
@N: MF138 :"f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\change.v":66:8:66:11|Rom seven_13[6:0] mapped in logic.
@N: MO106 :"f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\change.v":66:8:66:11|Found ROM, 'seven_13[6:0]', 9 words by 7 bits 
@N: MT204 |Autoconstrain Mode is ON
RTL optimization done.
@N: MF179 :|Found 16 bit by 16 bit '==' comparator, 'addre224'
@N: MF179 :|Found 16 bit by 16 bit '==' comparator, 'y18'
@N: MF179 :|Found 15 bit by 15 bit '==' comparator, 'un1_addre1_2'
@N: MF179 :|Found 15 bit by 15 bit '==' comparator, 'un1_addre1_1'
@N:"f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\buttonte.v":127:1:127:6|Found counter in view:work.buttonte(verilog) inst count3[8:0]
@N:"f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\buttonte.v":93:1:93:6|Found counter in view:work.buttonte(verilog) inst count2[8:0]
@N:"f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\buttonte.v":58:0:58:5|Found counter in view:work.buttonte(verilog) inst count1[8:0]
@N:"f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\buttonte.v":23:0:23:5|Found counter in view:work.buttonte(verilog) inst count0[8:0]
Automatic dissolve during optimization of view:work.vga_key(verilog) of m1(vga)

Clock Buffers:
  Inserting Clock buffer for port clk,	TNM=clk
  Inserting Clock buffer on net m2.clkout, 	TNM=m2_clkout

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:0m:19s		    -1.90ns		 568 /       244
   2		0h:0m:19s		    -1.90ns		 568 /       244
   3		0h:0m:19s		    -1.90ns		 568 /       244
------------------------------------------------------------

Timing driven replication report
@N: FX235 :"f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\buttonte.v":143:0:143:5|Instance "m2.m2.bn3[0]" with 5 loads has been replicated 1 time(s) to improve timing 
@N: FX235 :"f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v":63:0:63:5|Instance "m1.m2.addre1[2]" with 8 loads has been replicated 1 time(s) to improve timing 
@N: FX235 :"f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v":63:0:63:5|Instance "m1.m2.addre1[3]" with 8 loads has been replicated 1 time(s) to improve timing 
@N: FX235 :"f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v":63:0:63:5|Instance "m1.m2.addre1[0]" with 8 loads has been replicated 1 time(s) to improve timing 
@N: FX235 :"f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v":63:0:63:5|Instance "m1.m2.addre1[1]" with 8 loads has been replicated 1 time(s) to improve timing 
@N: FX235 :"f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\buttonte.v":151:4:151:5|Instance "m2.m2.bn3_5[0]" with 2 loads has been replicated 1 time(s) to improve timing 
Added 5 Registers via timing driven replication
Added 1 LUTs via timing driven replication

Timing driven replication report
No replication required.

Timing driven replication report
@N: FX235 :"f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v":63:0:63:5|Instance "m1.m2.addre1[4]" with 8 loads has been replicated 1 time(s) to improve timing 
@N: FX235 :"f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v":63:0:63:5|Instance "m1.m2.addre1[7]" with 10 loads has been replicated 1 time(s) to improve timing 
@N: FX235 :"f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v":63:0:63:5|Instance "m1.m2.addre1[8]" with 9 loads has been replicated 1 time(s) to improve timing 
@N: FX235 :"f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v":63:0:63:5|Instance "m1.m2.addre1[5]" with 9 loads has been replicated 1 time(s) to improve timing 
@N: FX235 :"f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v":63:0:63:5|Instance "m1.m2.addre1[6]" with 9 loads has been replicated 1 time(s) to improve timing 
Added 5 Registers via timing driven replication
Added 0 LUTs via timing driven replication

Timing driven replication report
No replication required.

Timing driven replication report
@N: FX235 :"f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\vs_hs.v":16:0:16:5|Instance "m1.m1.countvs[1]" with 5 loads has been replicated 1 time(s) to improve timing 
@N: FX235 :"f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\vs_hs.v":16:0:16:5|Instance "m1.m1.countvs[2]" with 5 loads has been replicated 1 time(s) to improve timing 
@N: FX235 :"f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\vs_hs.v":16:0:16:5|Instance "m1.m1.countvs[3]" with 5 loads has been replicated 1 time(s) to improve timing 
Added 3 Registers via timing driven replication
Added 0 LUTs via timing driven replication

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:0m:24s		    -3.72ns		 623 /       257