vs_hs.v

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`timescale 1ns / 1ps

module vs_hs(clk, rst,hs,vs,counths,countvs);
    input clk;
	 input rst;
    output hs;
	 output vs;
	 output [9:0] counths;
	 output [9:0] countvs;
    reg hs;
	 reg vs;
	 reg  [9:0] counths;
	 reg  [9:0] countvs;


always@( posedge clk or negedge rst)
 begin
   if(!rst)  
	   begin
	   counths<=799;
		countvs<=521;
		end
   else
	  begin
	    if(counths==799)
		     begin
		     counths<=0;
			    begin
				   if(countvs==521)
					   countvs<=0;
					else
				      countvs<=countvs+1;
				 end
			  
			  end
			  
		 else
           counths<=counths+1;  

      end
 end
 
 
always@( posedge clk or negedge rst)
 begin
   if(!rst) 
      hs<=0;
	else
     begin
       if(counths<96)
		  hs<=0;         
       else
		  hs<=1;
     end
 end	


always@( posedge clk or negedge rst)
 begin
   if(!rst)  
      vs<=0; 
	else
     begin
       if(countvs<2)
         vs<=0;         
       else
         vs<=1;
     end
 end	
	
endmodule