clkdiv.v

来自「利用VERILOG编写的基于XILINX的SPARTAN板的VGA接口显示程序」· Verilog 代码 · 共 26 行

`timescale 1ns / 1ps

module clkdiv(clk, rst, clkout);
    input clk;
    input rst;
    output clkout;
	// wire clkout;
	 reg [14:0] count16;
	 
always @(posedge clk or negedge rst)
 begin
   if(!rst)
      count16<=0;
   else
      begin
        if(count16==25000)
          count16<=0;
        else
          count16<=count16+1;
      end
 end
 
assign clkout=count16[14];

endmodule