vga_key_pad.txt
来自「利用VERILOG编写的基于XILINX的SPARTAN板的VGA接口显示程序」· 文本 代码 · 共 175 行 · 第 1/3 页
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Release 8.2.03i - par I.34Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.Sat May 03 16:15:21 2008INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:1. The <design name>_pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors.2. The <design namd>_pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information.3. The <design name>.pad file designed for parsing by customers. It uses the "|" as a data field separator.INPUT FILE: vga_key_map.ncdOUTPUT FILE: vga_key_pad.txtPART TYPE: xc3s100eSPEED GRADE: -4PACKAGE: tq144Pinout by Pin Number:+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+|Pin Number|Signal Name|Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage |Constraint|DCI Value|IO Register|Signal Integrity|+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+|P1 | | |PROG_B | | | | | | | | | | | | ||P2 | |DIFFM |IO_L01P_3 |UNUSED | |3 | | | | | | | | | ||P3 | |DIFFS |IO_L01N_3 |UNUSED | |3 | | | | | | | | | ||P4 | |DIFFM |IO_L02P_3 |UNUSED | |3 | | | | | | | | | ||P5 | |DIFFS |IO_L02N_3/VREF_3 |UNUSED | |3 | | | | | | | | | ||P6 | |IBUF |IP |UNUSED | |3 | | | | | | | | | ||P7 | |DIFFM |IO_L03P_3 |UNUSED | |3 | | | | | | | | | ||P8 | |DIFFS |IO_L03N_3 |UNUSED | |3 | | | | | | | | | ||P9 | | |VCCINT | | | | | | | |1.2 | | | | ||P10 | |IOB |IO |UNUSED | |3 | | | | | | | | | ||P11 | | |GND | | | | | | | | | | | | ||P12 | |IBUF |IP/VREF_3 |UNUSED | |3 | | | | | | | | | ||P13 | | |VCCO_3 | | |3 | | | | |2.50 | | | | ||P14 | |DIFFM |IO_L04P_3/LHCLK0 |UNUSED | |3 | | | | | | | | | ||P15 | |DIFFS |IO_L04N_3/LHCLK1 |UNUSED | |3 | | | | | | | | | ||P16 |seven[1] |IOB |IO_L05P_3/LHCLK2 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE ||P17 |seven[5] |IOB |IO_L05N_3/LHCLK3/IRDY2 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE ||P18 | |IBUF |IP |UNUSED | |3 | | | | | | | | | ||P19 | | |GND | | | | | | | | | | | | ||P20 |seven[4] |IOB |IO_L06P_3/LHCLK4/TRDY2 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE ||P21 |seven[3] |IOB |IO_L06N_3/LHCLK5 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE ||P22 | |DIFFM |IO_L07P_3/LHCLK6 |UNUSED | |3 | | | | | | | | | ||P23 |seven[2] |IOB |IO_L07N_3/LHCLK7 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE ||P24 | |IBUF |IP |UNUSED | |3 | | | | | | | | | ||P25 |seven[0] |IOB |IO_L08P_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE ||P26 |ea[3] |IOB |IO_L08N_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE ||P27 | | |GND | | | | | | | | | | | | ||P28 | | |VCCO_3 | | |3 | | | | |2.50 | | | | ||P29 | |IOB |IO |UNUSED | |3 | | | | | | | | | ||P30 | | |VCCAUX | | | | | | | |2.5 | | | | ||P31 | |IBUF |IP/VREF_3 |UNUSED | |3 | | | | | | | | | ||P32 |ea[2] |IOB |IO_L09P_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE ||P33 |ea[1] |IOB |IO_L09N_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE ||P34 |ea[0] |IOB |IO_L10P_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE ||P35 |vs |IOB |IO_L10N_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE ||P36 |sw2 |IBUF |IP |INPUT |LVCMOS25 |3 | | | |NONE | |LOCATED | |NO |NONE ||P37 | | |GND | | | | | | | | | | | | |
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