buttonte.v

来自「利用VERILOG编写的基于XILINX的SPARTAN板的VGA接口显示程序」· Verilog 代码 · 共 212 行

`timescale 1ns / 1ps

module buttonte(clkout, rst, button, bn0, bn1, bn2, bn3);
    input clkout;
    input rst;
    input [3:0] button;
    output [3:0] bn0;
    output [3:0] bn1;
    output [3:0] bn2;
    output [3:0] bn3;
	 reg   [3:0] bn0;
	 reg   [3:0] bn1;
	 reg   [3:0] bn2;
	 reg   [3:0] bn3;
	 reg  [8:0] count0;
	 reg  [8:0] count1;
	 reg  [8:0] count2;
	 reg  [8:0] count3;
	 
	 

	 
always @(posedge clkout or negedge rst)
 begin 
    if(!rst)
	   begin
		 
		  count0<=0;
		end
	 else
	   begin
		 if(button[0]==1)
		   count0<=count0+1; 
		 else
		   count0<=0;
		end
 end
 
always @(posedge clkout or negedge rst)
 begin 
    if(!rst) 
	  bn0<=0;
	 else
	  begin
	   if(count0==30)
		  begin
		  if(bn0==9)
		    bn0<=0;
		  else
		    bn0<=bn0+1;
		  end	
	  end
 end

        		


always @(posedge clkout or negedge rst)
 begin 
    if(!rst)
	   begin
		 
		  count1<=0;
		end
	 else
	   begin
		 if(button[1]==1)
		   count1<=count1+1; 
		 else
		   count1<=0;
		end
 end
 
always @(posedge clkout or negedge rst)
 begin 
    if(!rst) 
	  bn1<=0;
	 else
	  begin
	   if(count1==30)
		  begin
		  if(bn1==9)
		    bn1<=0;
		  else
		    bn1<=bn1+1;
		  end	
	  end
 end
 
 
 
 
 always @(posedge clkout or negedge rst)
 begin 
    if(!rst)
	   begin
		 
		  count2<=0;
		end
	 else
	   begin
		 if(button[2]==1)
		   count2<=count2+1; 
		 else
		   count2<=0;
		end
 end
 
always @(posedge clkout or negedge rst)
 begin 
    if(!rst) 
	  bn2<=0;
	 else
	  begin
	   if(count2==30)
		  begin
		  if(bn2==9)
		    bn2<=0;
		  else
		    bn2<=bn2+1;
		  end	
	  end
 end
 
 
 
 always @(posedge clkout or negedge rst)
 begin 
    if(!rst)
	   begin
		 
		  count3<=0;
		end
	 else
	   begin
		 if(button[3]==1)
		   count3<=count3+1; 
		 else
		   count3<=0;
		end
 end
 
always @(posedge clkout or negedge rst)
 begin 
    if(!rst) 
	  bn3<=0;
	 else
	  begin
	   if(count3==30)
		  begin
		  if(bn3==4)
		    bn3<=0;
		  else
		    bn3<=bn3+1;
		  end	
	  end
 end
/*
always @(posedge button[0] or negedge rst)
 begin 
    if(!rst)
      bn0<=0;
    else
      begin
		  if(bn0==9)
		    bn0<=0;
		  else
		   bn0<=bn0+1;
		end
 end

always @(posedge button[1] or negedge rst)
 begin 
    if(!rst)
      bn1<=0;
    else
      begin
		  if(bn1==9)
		    bn1<=0;
		  else
		   bn1<=bn1+1;
		end
 end
 
 always @(posedge button[2] or negedge rst)
 begin 
    if(!rst)
      bn2<=0;
    else
      begin
		  if(bn2==9)
		    bn2<=0;
		  else
		   bn2<=bn2+1;
		end
 end
 
 always @(posedge button[3] or negedge rst)
 begin 
    if(!rst)
      bn3<=0;
    else
      begin
		  if(bn3==9)
		    bn3<=0;
		  else
		   bn3<=bn3+1;
		end
 end
*/
endmodule