sendsave.v

来自「利用VERILOG编写的基于XILINX的SPARTAN板的VGA接口显示程序」· Verilog 代码 · 共 88 行

`timescale 1ns / 1ps

module sendsave(clk,rst,ssra,sw2, addr, din,  wea);
    input clk;
	 input rst;
	 input sw2;
    output [14:0] addr;
    output din;
    output wea;
	 output ssra;
	 reg  din;
	 reg wea;
	 reg ssra;
	// reg [19:0] count;
	 reg  [14:0] addr;
	 
	 
//assign wea=0;	
//assign ena=1; 
//assign din=1;

always@( posedge clk or negedge rst)
 begin
   if(!rst) 
	 ssra<=1;
	 else
	   begin
		  if(sw2==1)
		    begin
			 ssra<=0;
			 wea<=0;
			 end
		   else
			 begin
			 ssra<=1;
		    wea<=1;
          end			 
		end
 end


always@( posedge clk or negedge rst)
 begin
   if(!rst) 
	  addr<=19199;
	else
	  begin
	    if(addr==19199)
		    addr<=0;
		 else
		    addr<=addr+1;
	  end
 end


/*always@( posedge clk or negedge rst)
 begin
   if(!rst)
	 count<=416800;
	else
	  begin
	    if(count==416800)
		   count<=0;
		 else
		   count<=count+1;
		end
 end

*/







always@( posedge clk or negedge rst)
 begin
   if(!rst) 
	  din<=0;
	else
	  din<=1;
end



endmodule