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📄 vga_key.srs

📁 利用VERILOG编写的基于XILINX的SPARTAN板的VGA接口显示程序
💻 SRS
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123 
#
#
#
# Created by Synplify Verilog HDL Compiler version 3.1.0, Build 049R from Synplicity, Inc.
# Copyright 1994-2004 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Sat May 03 16:17:43 2008
#
#
#OPTIONS:"|-top|vga_key|-primux|-fixsmult|-sdff_counter|-infer_seqShift|-nram|-divnmod|-I|F:\\basys\\basys\\huanyizuoyi17\\huanyizuoyi\\VGAVGA\\|-I|d:\\Program Files\\Synplicity\\fpga_81\\lib|-v2001|-devicelib|d:\\Program Files\\Synplicity\\fpga_81\\lib\\xilinx\\unisim.v|-autosm|-fid2|-sharing|on|-encrypt|-ui|-pro|-ram|-ll|2000"
#CUR:"d:\\Program Files\\Synplicity\\fpga_81\\bin\\c_ver.exe":1115125636
#CUR:"d:\\Program Files\\Synplicity\\fpga_81\\lib\\xilinx\\unisim.v":1113287638
#CUR:"d:\\Program Files\\Synplicity\\fpga_81\\lib\\xilinx\\unisim.v":1113287638
#CUR:"d:\\Program Files\\Synplicity\\fpga_81\\bin\\..\\lib\\xilinx\\unisim.v":1113287638
#CUR:"d:\\Program Files\\Synplicity\\fpga_81\\bin\\..\\lib\\xilinx\\unisim.v":1113287638
#CUR:"F:\\basys\\basys\\huanyizuoyi17\\huanyizuoyi\\VGAVGA\\vs_hs.v":1209802620
#CUR:"F:\\basys\\basys\\huanyizuoyi17\\huanyizuoyi\\VGAVGA\\vs_hs.v":1209802620
#CUR:"F:\\basys\\basys\\huanyizuoyi17\\huanyizuoyi\\VGAVGA\\sendsave.v":1209802620
#CUR:"F:\\basys\\basys\\huanyizuoyi17\\huanyizuoyi\\VGAVGA\\sendsave.v":1209802620
#CUR:"F:\\basys\\basys\\huanyizuoyi17\\huanyizuoyi\\VGAVGA\\savecon.v":1209802620
#CUR:"F:\\basys\\basys\\huanyizuoyi17\\huanyizuoyi\\VGAVGA\\savecon.v":1209802620
#CUR:"F:\\basys\\basys\\huanyizuoyi17\\huanyizuoyi\\VGAVGA\\save.v":1195286898
#CUR:"F:\\basys\\basys\\huanyizuoyi17\\huanyizuoyi\\VGAVGA\\save.v":1195286898
#CUR:"F:\\basys\\basys\\huanyizuoyi17\\huanyizuoyi\\VGAVGA\\clkdiv.v":1209802621
#CUR:"F:\\basys\\basys\\huanyizuoyi17\\huanyizuoyi\\VGAVGA\\clkdiv.v":1209802621
#CUR:"F:\\basys\\basys\\huanyizuoyi17\\huanyizuoyi\\VGAVGA\\change.v":1209802623
#CUR:"F:\\basys\\basys\\huanyizuoyi17\\huanyizuoyi\\VGAVGA\\change.v":1209802623
#CUR:"F:\\basys\\basys\\huanyizuoyi17\\huanyizuoyi\\VGAVGA\\buttonte.v":1209802622
#CUR:"F:\\basys\\basys\\huanyizuoyi17\\huanyizuoyi\\VGAVGA\\buttonte.v":1209802622
#CUR:"F:\\basys\\basys\\huanyizuoyi17\\huanyizuoyi\\VGAVGA\\vga.v":1209802619
#CUR:"F:\\basys\\basys\\huanyizuoyi17\\huanyizuoyi\\VGAVGA\\vga.v":1209802619
#CUR:"F:\\basys\\basys\\huanyizuoyi17\\huanyizuoyi\\VGAVGA\\key_display.v":1209802621
#CUR:"F:\\basys\\basys\\huanyizuoyi17\\huanyizuoyi\\VGAVGA\\key_display.v":1209802621
#CUR:"F:\\basys\\basys\\huanyizuoyi17\\huanyizuoyi\\VGAVGA\\vga_key.v":1209802616
#CUR:"F:\\basys\\basys\\huanyizuoyi17\\huanyizuoyi\\VGAVGA\\vga_key.v":1209802616
f "d:\Program Files\Synplicity\fpga_81\lib\xilinx\unisim.v"; # file 0
af .is_verilog 1;
f "d:\Program Files\Synplicity\fpga_81\bin\..\lib\xilinx\unisim.v"; # file 1
af .is_verilog 1;
f "F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\vs_hs.v"; # file 2
af .is_verilog 1;
f "F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\sendsave.v"; # file 3
af .is_verilog 1;
f "F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v"; # file 4
af .is_verilog 1;
f "F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\save.v"; # file 5
af .is_verilog 1;
f "F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\clkdiv.v"; # file 6
af .is_verilog 1;
f "F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\change.v"; # file 7
af .is_verilog 1;
f "F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\buttonte.v"; # file 8
af .is_verilog 1;
f "F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\vga.v"; # file 9
af .is_verilog 1;
f "F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\key_display.v"; # file 10
af .is_verilog 1;
f "F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\vga_key.v"; # file 11
af .is_verilog 1;
@E
@ 
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