traplog.tlg

来自「利用VERILOG编写的基于XILINX的SPARTAN板的VGA接口显示程序」· TLG 代码 · 共 19 行

@N:".\gentmp0a01616":4:7:4:9|Synthesizing work.top.gen 
@N:"syng0a01616":73:7:73:12|Synthesizing work.cmp_eq.cell_level 
@W:"syng0a01616":96:11:96:18|Bit <7> of signal data_tmp is undriven 
@W:"syng0a01616":96:11:96:18|Bit <8> of signal data_tmp is undriven 
@W:"syng0a01616":96:11:96:18|Bit <9> of signal data_tmp is undriven 
@W:"syng0a01616":96:11:96:18|Bit <10> of signal data_tmp is undriven 
@W:"syng0a01616":96:11:96:18|Bit <11> of signal data_tmp is undriven 
@W:"syng0a01616":96:11:96:18|Bit <12> of signal data_tmp is undriven 
@W:"syng0a01616":96:11:96:18|Bit <13> of signal data_tmp is undriven 
@W:"syng0a01616":96:11:96:18|Bit <14> of signal data_tmp is undriven 
@N:"syng0a01616":41:7:41:23|Synthesizing work.eq_element_onebit.eqn 
@N:"d:\Program Files\Synplicity\fpga_81\lib\xilinx\unisim.vhd":11281:10:11281:16|Synthesizing unisim.muxcy_l.syn_black_box 
Post processing for unisim.muxcy_l.syn_black_box
Post processing for work.eq_element_onebit.eqn
@N:"syng0a01616":8:7:8:16|Synthesizing work.eq_element.eqn 
Post processing for work.eq_element.eqn
Post processing for work.cmp_eq.cell_level
Post processing for work.top.gen