vgatest.ant

来自「利用VERILOG编写的基于XILINX的SPARTAN板的VGA接口显示程序」· ANT 代码 · 共 159 行

////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2003 Xilinx, Inc.
// All Right Reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /    Vendor: Xilinx 
// \   \   \/     Version : 8.2i
//  \   \         Application : ISE
//  /   /         Filename : vgatest.ant
// /___/   /\     Timestamp : Wed Nov 14 18:54:28 2007
// \   \  /  \ 
//  \___\/\___\ 
//
//Command: 
//Design Name: vgatest
//Device: Xilinx
//
`timescale 1ns/1ps

module vgatest;
    reg clk = 1'b0;
    reg rst = 1'b0;
    reg sw2 = 1'b0;
    reg sw3 = 1'b0;
    wire hs;
    wire vs;
    wire [2:0] red;
    wire [2:0] green;
    wire [1:0] blue;
    wire [14:0] addrb;

    parameter PERIOD = 40;
    parameter real DUTY_CYCLE = 0.5;
    parameter OFFSET = 0;

    initial    // Clock process for clk
    begin
        #OFFSET;
        forever
        begin
            clk = 1'b0;
            #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
            #(PERIOD*DUTY_CYCLE);
        end
    end

    vga UUT (
        .clk(clk),
        .rst(rst),
        .sw2(sw2),
        .sw3(sw3),
        .hs(hs),
        .vs(vs),
        .red(red),
        .green(green),
        .blue(blue),
        .addrb(addrb));

    integer TX_FILE = 0;
    integer TX_ERROR = 0;
    
    initial begin    // Annotation process for clock clk
        #0;
        ANNOTATE_hs;
        ANNOTATE_vs;
        ANNOTATE_red;
        ANNOTATE_green;
        ANNOTATE_blue;
        ANNOTATE_addrb;
        #OFFSET;
        forever begin
            #23;
            ANNOTATE_hs;
            ANNOTATE_vs;
            ANNOTATE_red;
            ANNOTATE_green;
            ANNOTATE_blue;
            ANNOTATE_addrb;
            #17;
        end
    end

    initial begin  // Open the annotations file...
        TX_FILE = $fopen("D:\\Xilinx\\basys\\VGAVGA\\vgatest.ano");
        #1.00004e+006 // Final time:  1.00004e+006 ns
        $display("Success! Annotation Simulation Complete.");
        $fdisplay(TX_FILE, "Total[%d]", TX_ERROR);
        $fclose(TX_FILE);
        $finish;
    end

    initial begin
        // -------------  Current Time:  17ns
        #17;
        rst = 1'b1;
        // -------------------------------------
        // -------------  Current Time:  999017ns
        #999000;
        rst = 1'b0;
        // -------------------------------------
        // -------------  Current Time:  999057ns
        #40;
        rst = 1'b1;
        sw3 = 1'b1;
        // -------------------------------------
    end

    task ANNOTATE_hs;
        #0 begin
            $fdisplay(TX_FILE, "Annotate[%d,hs,%b]", $time, hs);
            $fflush(TX_FILE);
            TX_ERROR = TX_ERROR + 1;
        end
    endtask

    task ANNOTATE_vs;
        #0 begin
            $fdisplay(TX_FILE, "Annotate[%d,vs,%b]", $time, vs);
            $fflush(TX_FILE);
            TX_ERROR = TX_ERROR + 1;
        end
    endtask

    task ANNOTATE_red;
        #0 begin
            $fdisplay(TX_FILE, "Annotate[%d,red,%b]", $time, red);
            $fflush(TX_FILE);
            TX_ERROR = TX_ERROR + 1;
        end
    endtask

    task ANNOTATE_green;
        #0 begin
            $fdisplay(TX_FILE, "Annotate[%d,green,%b]", $time, green);
            $fflush(TX_FILE);
            TX_ERROR = TX_ERROR + 1;
        end
    endtask

    task ANNOTATE_blue;
        #0 begin
            $fdisplay(TX_FILE, "Annotate[%d,blue,%b]", $time, blue);
            $fflush(TX_FILE);
            TX_ERROR = TX_ERROR + 1;
        end
    endtask

    task ANNOTATE_addrb;
        #0 begin
            $fdisplay(TX_FILE, "Annotate[%d,addrb,%b]", $time, addrb);
            $fflush(TX_FILE);
            TX_ERROR = TX_ERROR + 1;
        end
    endtask

endmodule