save.xco

利用VERILOG编写的基于XILINX的SPARTAN板的VGA接口显示程序

# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\Xilinx\basys\VGA1\VGA
SET speedgrade = -4
SET simulationfiles = Behavioral
SET asysymbol = True
SET addpads = False
SET device = xc3s100e
SET implementationfiletype = ngc
SET busformat = BusFormatAngleBracketNotRipped
SET foundationsym = False
SET package = tq144
SET createndf = False
SET designentry = VHDL
SET devicefamily = spartan3e
SET formalverification = False
SET removerpms = False
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator family Xilinx,_Inc. 1.1
# END Select
# BEGIN Parameters
CSET write_depth_a=19200
CSET operating_mode_a=NO_CHANGE
CSET operating_mode_b=NO_CHANGE
CSET write_width_a=1
CSET write_width_b=1
CSET use_regcea_pin=false
CSET primitive=8kx2
CSET memory_type=True_Dual_Port_RAM
CSET byte_size=9
CSET disable_out_of_range_warnings=false
CSET use_regceb_pin=false
CSET remaining_memory_locations=0
CSET use_byte_write_enable=false
CSET enable_a=Always_Enabled
CSET enable_b=Always_Enabled
CSET component_name=save
CSET assume_synchronous_clk=false
CSET disable_collision_warnings=false
CSET algorithm=Minimum_Area
CSET fill_remaining_memory_locations=true
CSET register_output_of_memory_primitives=false
CSET use_ssra_pin=true
CSET read_width_a=1
CSET read_width_b=1
CSET register_output_of_memory_core=false
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET load_init_file=true
CSET coe_file=D:/Xilinx/basys/memme17.coe
CSET use_ssrb_pin=false
CSET collision_warnings=ALL
# END Parameters
GENERATE