vga_srr.htm

利用VERILOG编写的基于XILINX的SPARTAN板的VGA接口显示程序

   2		0h:0m:10s		    -0.13ns		 283 /       119
   3		0h:0m:10s		    -0.13ns		 283 /       119
Timing driven replication report
No replication required.

   4		0h:0m:10s		    -0.13ns		 283 /       119
   5		0h:0m:10s		    -0.13ns		 283 /       119
   6		0h:0m:10s		    -0.13ns		 283 /       119
------------------------------------------------------------

Timing driven replication report
No replication required.

Timing driven replication report
No replication required.

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:0m:10s		    -2.88ns		 283 /       119
   2		0h:0m:10s		    -2.88ns		 283 /       119
   3		0h:0m:10s		    -2.88ns		 283 /       119
Timing driven replication report
No replication required.

   4		0h:0m:10s		    -2.88ns		 283 /       119
   5		0h:0m:10s		    -2.88ns		 283 /       119
   6		0h:0m:10s		    -2.88ns		 283 /       119
------------------------------------------------------------

Net buffering Report for view:work.vga(verilog):
No nets needed buffering.

@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1195174176> | The option to pack flops in the IOB has not been specified  
Writing Analyst data base D:\Xilinx\basys\huanyizuoyi\VGAVGA\vga.srm
Writing EDIF Netlist and constraint files
Found clock vga|clk with period 8.11ns 
<font color=#A52A2A>@W:<a href="@W:MT253:@XP_HELP">MT253</a> : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\vga.v:51:5:51:7:@W:MT253:@XP_MSG">vga.v(51)</a><!@TM:1195174176> | Blackbox save is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) </font>


<a name=timingReport3>##### START OF TIMING REPORT #####[
# Timing Report written on Fri Nov 16 08:49:34 2007
#


Top view:               vga
Requested Frequency:    123.2 MHz
Wire load mode:         top
Paths requested:        0
Constraint File(s):    D:\Xilinx\basys\huanyizuoyi\VGAVGA\vga.sdc
                       
@N:<a href="@N:MT195:@XP_HELP">MT195</a> : <!@TM:1195174176> | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. 

@N:<a href="@N:MT197:@XP_HELP">MT197</a> : <!@TM:1195174176> | Clock constraints cover only FF-to-FF paths associated with the clock.. 



<a name=performanceSummary4>Performance Summary 
*******************


Worst slack in design: -1.432

                   Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group                
------------------------------------------------------------------------------------------------------------------------
vga|clk            123.2 MHz     104.8 MHz     8.114         9.546         -1.432     inferred     Autoconstr_clkgroup_0
========================================================================================================================





<a name=clockRelationships5>Clock Relationships
*******************

Clocks             |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
----------------------------------------------------------------------------------------------------------
Starting  Ending   |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
----------------------------------------------------------------------------------------------------------
vga|clk   vga|clk  |  8.114       -1.432  |  No paths    -      |  No paths    -      |  No paths    -    
==========================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



<a name=interfaceInfo6>Interface Information 
*********************

		No IO constraint found 


##### END OF TIMING REPORT #####]

---------------------------------------
<a name=resourceUsage7>Resource Usage Report for vga 

Mapping to part: xc3s100etq144-4
Cell usage:
FDC             25 uses
FDCE            59 uses
FDE             2 uses
FDP             33 uses
GND             4 uses
MUXCY           5 uses
MUXCY_L         110 uses
VCC             4 uses
XORCY           96 uses
save            1 use
LUT1            103 uses
LUT2            60 uses
LUT3            20 uses
LUT4            96 uses

I/O primitives: 28
IBUF           3 uses
OBUF           25 uses

BUFGP          1 use

I/O Register bits:                  0
Register bits not including I/Os:   119 (4%)

Global Clock Buffers: 1 of 24 (4%)


Mapping Summary:
Total  LUTs: 279 (9%)

Mapper successful!
Process took 0h:0m:12s realtime, 0h:0m:12s cputime
###########################################################]