save.v

利用VERILOG编写的基于XILINX的SPARTAN板的VGA接口显示程序

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// The synopsys directives "translate_off/translate_on" specified below are
// supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).

// You must compile the wrapper file save.v when simulating
// the core, save. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".

`timescale 1ns/1ps

module save(
	clka,
	dina,
	addra,
	wea,
	ssra,
	douta,
	clkb,
	dinb,
	addrb,
	web,
	doutb);


input clka;
input [0 : 0] dina;
input [14 : 0] addra;
input [0 : 0] wea;
input ssra;
output [0 : 0] douta;
input clkb;
input [0 : 0] dinb;
input [14 : 0] addrb;
input [0 : 0] web;
output [0 : 0] doutb;

// synopsys translate_off

      BLK_MEM_GEN_V1_1 #(
		15,	// c_addra_width
		15,	// c_addrb_width
		1,	// c_algorithm
		9,	// c_byte_size
		0,	// c_common_clk
		"0",	// c_default_data
		0,	// c_disable_warn_bhv_coll
		0,	// c_disable_warn_bhv_range
		"spartan3",	// c_family
		0,	// c_has_ena
		0,	// c_has_enb
		0,	// c_has_mem_output_regs
		0,	// c_has_mux_output_regs
		0,	// c_has_regcea
		0,	// c_has_regceb
		1,	// c_has_ssra
		0,	// c_has_ssrb
		"save.mif",	// c_init_file_name
		1,	// c_load_init_file
		2,	// c_mem_type
		1,	// c_prim_type
		19200,	// c_read_depth_a
		19200,	// c_read_depth_b
		1,	// c_read_width_a
		1,	// c_read_width_b
		"ALL",	// c_sim_collision_check
		"0",	// c_sinita_val
		"0",	// c_sinitb_val
		0,	// c_use_byte_wea
		0,	// c_use_byte_web
		1,	// c_use_default_data
		1,	// c_wea_width
		1,	// c_web_width
		19200,	// c_write_depth_a
		19200,	// c_write_depth_b
		"NO_CHANGE",	// c_write_mode_a
		"NO_CHANGE",	// c_write_mode_b
		1,	// c_write_width_a
		1)	// c_write_width_b
	inst (
		.CLKA(clka),
		.DINA(dina),
		.ADDRA(addra),
		.WEA(wea),
		.SSRA(ssra),
		.DOUTA(douta),
		.CLKB(clkb),
		.DINB(dinb),
		.ADDRB(addrb),
		.WEB(web),
		.DOUTB(doutb),
		.ENA(),
		.REGCEA(),
		.ENB(),
		.REGCEB(),
		.SSRB());


// synopsys translate_on

// FPGA Express black box declaration
// synopsys attribute fpga_dont_touch "true"
// synthesis attribute fpga_dont_touch of save is "true"

// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of save is "black_box"

endmodule