par.xmsgs

来自「利用VERILOG编写的基于XILINX的SPARTAN板的VGA接口显示程序」· XMSGS 代码 · 共 17 行

<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
     by the Xilinx ISE software.  Any direct editing or
     changes made to this file may result in unpredictable
     behavior or data corruption.  It is strongly advised that
     users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Par" num="62" delta="unknown" >Your design did not meet timing.  The following are some suggestions to assist you to meet timing in your design.

   Review the timing report using Timing Analyzer (In ISE select &quot;Post-Place &amp;
   Route Static Timing Report&quot;).  Go to the failing constraint(s) and select
   the &quot;Timing Improvement Wizard&quot; link for suggestions to correct each problem.

</msg>

</messages>