c8plant.mdl

包含大量遗传算法程序

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		Cell			"IncludeMdlTerminateFcn"
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		Cell			"ERTCustomFileBanners"
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		Cell			"SupportNonInlinedSFcns"
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	      Version		      "1.0.4"
	      TargetFcnLib	      "ansi_tfl_tmw.mat"
	      GenFloatMathFcnCalls    "ANSI_C"
	      UtilityFuncGeneration   "Auto"
	      GenerateFullHeader      on
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	      ExtModeStaticAlloc      off
	      ExtModeTesting	      off
	      ExtModeStaticAllocSize  1000000
	      ExtModeTransport	      0
	      ExtModeMexFile	      "ext_comm"
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      Name		      "Configuration"
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      CurrentDlgPage	      "Solver"
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    Orientation		    "right"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
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    NamePlacement	    "normal"
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
    ShowName		    on
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  BlockParameterDefaults {
    Block {
      BlockType		      Clock
      DisplayTime	      off
    }
    Block {
      BlockType		      Fcn
      Expr		      "sin(u[1])"
      SampleTime	      "-1"
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    Block {
      BlockType		      Inport
      BusObject		      "BusObject"
      BusOutputAsStruct	      off
      PortDimensions	      "-1"
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      BusObject		      "BusObject"
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      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      SignalType	      "auto"
      SamplingMode	      "auto"
      OutputWhenDisabled      "held"
      InitialOutput	      "[]"
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      BlockType		      Product
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      Multiplication	      "Element-wise(.*)"
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      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      LockScale		      off
      RndMeth		      "Zero"
      SaturateOnIntegerOverflow	on
      SampleTime	      "-1"
    }
    Block {
      BlockType		      Sum
      IconShape		      "rectangular"
      Inputs		      "++"
      InputSameDT	      on
      OutDataTypeMode	      "Same as first input"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      LockScale		      off
      RndMeth		      "Floor"
      SaturateOnIntegerOverflow	on
      SampleTime	      "-1"
    }
    Block {
      BlockType		      UnitDelay
      X0		      "0"
      SampleTime	      "1"
      StateMustResolveToSignalObject off
      RTWStateStorageClass    "Auto"
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  }
  AnnotationDefaults {
    HorizontalAlignment	    "center"
    VerticalAlignment	    "middle"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  LineDefaults {
    FontName		    "Helvetica"
    FontSize		    9
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  System {
    Name		    "c8plant"
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    PaperPositionMode	    "auto"
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      FontSize		      14
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    }
    Block {
      BlockType		      Fcn
      Name		      "Fcn"
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      FontName		      "Times New Roman"
      FontSize		      14
      Expr		      "a*(1-b*exp(-c*u/T))"
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      BlockType		      Product
      Name		      "Product"
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      Position		      [192, 145, 223, 170]
      Orientation	      "up"
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      BlockType		      Sum
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      FontSize		      14
      IconShape		      "round"
      Inputs		      "|++"
      InputSameDT	      off
      OutDataTypeMode	      "Inherit via internal rule"
    }
    Block {
      BlockType		      UnitDelay
      Name		      "Unit Delay1"
      Position		      [305, 185, 340, 225]
      Orientation	      "left"
      FontName		      "Times New Roman"
      FontSize		      14
      SampleTime	      "-1"
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      Name		      "Out1"
      Position		      [370, 103, 400, 117]
      FontName		      "Times New Roman"
      FontSize		      14
      IconDisplay	      "Port number"
      BusOutputAsStruct	      off
    }
    Line {
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      Points		      [-5, 0]
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      SrcBlock		      "Sum"
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      Branch {
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    Line {
      SrcBlock		      "Clock"
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}