test_comp_vhd.vhd

32位微处理器的设计

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-- Company: 
-- Engineer:
--
-- Create Date:   16:59:33 12/16/2007
-- Design Name:   comparer testbench
-- Module Name:   E:/ISEworkspace/RISC32/test_comp_vhd.vhd
-- Project Name:  RISC32
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: comparer
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;
use IEEE.std_logic_signed.ALL;

ENTITY test_comp_vhd_vhd IS
END test_comp_vhd_vhd;

ARCHITECTURE behavior OF test_comp_vhd_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT comparer
	port( en_comp:IN std_logic;
			comp_in1:IN signed(31 downto 0);
			comp_in2:IN signed(31 downto 0);
			comp_out:OUT signed(1 downto 0));
	END COMPONENT;

	--Inputs
	SIGNAL en_comp :  std_logic := '0';
	SIGNAL comp_in1 :  signed(31 downto 0) := (others=>'0');
	SIGNAL comp_in2 :  signed(31 downto 0) := (others=>'0');

	--Outputs
	SIGNAL comp_out :  signed(1 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: comparer PORT MAP(
		en_comp => en_comp,
		comp_in1 => comp_in1,
		comp_in2 => comp_in2,
		comp_out => comp_out
	);

--	tb : PROCESS
--	BEGIN

		comp_in1 <=X"00000002";
		comp_in2 <=X"00000000",X"00000004" after 10 ns,X"00000002" after 20 ns;
		en_comp <='0','1' after 5 ns;
--		wait;
--	END PROCESS;

END behavior;