test_cpu.vhd

32位微处理器的设计

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-- Company: 
-- Engineer:
--
-- Create Date:   16:58:44 12/18/2007
-- Design Name:   cpu
-- Module Name:   E:/ISEworkspace/RISC32/test_cpu.vhd
-- Project Name:  RISC32
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: cpu
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;
use IEEE.std_logic_signed.ALL;

ENTITY test_cpu_vhd IS
END test_cpu_vhd;

ARCHITECTURE behavior OF test_cpu_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT cpu
	PORT(
		clk : IN std_logic;
		data_in : IN signed(31 downto 0);
		reset : IN std_logic;          
		a : OUT signed(31 downto 0);
		r : OUT std_logic;
		do : OUT signed(31 downto 0);
		wb : OUT std_logic;
		ww : OUT std_logic
		);
	END COMPONENT;
	
	component mem
		port(di:in signed(31 downto 0);
			  do:out signed(31 downto 0);
			  a:in signed(31 downto 0);
			  clk,reset,ww,wb,r:in std_logic);
	end component;
	
	--Inputs
	SIGNAL clk :  std_logic := '0';
	SIGNAL reset :  std_logic := '1';
	signal r : std_logic;
	SIGNAL wb :  std_logic;
	SIGNAL ww :  std_logic;
	SIGNAL a :  signed(31 downto 0);
	signal cpudata_in:signed(31 downto 0);
	signal cpudata_out:signed(31 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut1: cpu PORT MAP(
		clk => clk,
		data_in => cpudata_in,
		reset => reset,
		a => a,
		r => r,
		do => cpudata_out,
		wb => wb,
		ww => ww
	);
	
	uut2:mem PORT MAP(
		di => cpudata_out,
		do => cpudata_in,
		a => a,
		clk => clk,
		reset => reset,
		ww => ww,
		wb => wb,
		r => r);
	
	PROCESS(clk)
	BEGIN
		clk<=not clk after 5 ns;
	end process;
	
	reset <='0' after 10 ns;
	
END;