muxa.vhd

32位微处理器的设计

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    22:32:14 12/17/2007 
-- Design Name: 
-- Module Name:    muxa - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use IEEE.std_logic_signed.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity muxa is
    Port ( rst : in  STD_LOGIC;
           muxa_c : in  STD_LOGIC;
           muxa_pc : in  signed (31 downto 0);
           muxa_aluout : in  signed (31 downto 0);
           muxa_out : out  signed (31 downto 0));
end muxa;

architecture Behavioral of muxa is

begin
	process(muxa_pc,muxa_aluout,muxa_c,rst)
	begin
		if (rst='1') then
			muxa_out <= X"80020000";
		else
			if (muxa_c='0') then
				muxa_out <= muxa_pc;
			else
				muxa_out <= muxa_aluout;
			end if;
		end if;
	end process;

end Behavioral;