muxalu2.vhd

32位微处理器的设计

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    22:44:34 12/17/2007 
-- Design Name: 
-- Module Name:    muxalu2 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
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-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use IEEE.std_logic_signed.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity muxalu2 is
    Port ( muxalu2_c : in  STD_LOGIC;
           muxalu2_rt : in  signed (31 downto 0);
           muxalu2_imm : in  signed (31 downto 0);
           muxalu2_out : out  signed (31 downto 0));
end muxalu2;

architecture Behavioral of muxalu2 is

begin
	process(muxalu2_rt,muxalu2_imm,muxalu2_c)
	begin
		case muxalu2_c is
			when '0' =>
				muxalu2_out <= muxalu2_imm;
			when '1' =>
				muxalu2_out <= muxalu2_rt;
			when others =>
				null;
		end case;
	end process;

end Behavioral;