tets_regfile_vhd.vhd

32位微处理器的设计

--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   14:18:32 12/17/2007
-- Design Name:   regfile
-- Module Name:   E:/ISEworkspace/RISC32/tets_regfile_vhd.vhd
-- Project Name:  RISC32
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: regfile
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;
use IEEE.std_logic_signed.ALL;

ENTITY tets_regfile_vhd_vhd IS
END tets_regfile_vhd_vhd;

ARCHITECTURE behavior OF tets_regfile_vhd_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT regfile
	PORT(
		clk : IN std_logic;
		reset : IN std_logic;
		en_wr : IN std_logic;
		en_r1 : IN std_logic;
		en_r2 : IN std_logic;
		wra : IN signed(4 downto 0);
		wrd : IN signed(31 downto 0);
		rra1 : IN signed(4 downto 0);
		rra2 : IN signed(4 downto 0);          
		rsd : OUT signed(31 downto 0);
		rtd : OUT signed(31 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL clk :  std_logic := '0';
	SIGNAL reset :  std_logic := '0';
	SIGNAL en_wr :  std_logic := '0';
	SIGNAL en_r1 :  std_logic := '0';
	SIGNAL en_r2 :  std_logic := '0';
	SIGNAL wra :  signed(4 downto 0) := (others=>'0');
	SIGNAL wrd :  signed(31 downto 0) := (others=>'0');
	SIGNAL rra1 :  signed(4 downto 0) := (others=>'0');
	SIGNAL rra2 :  signed(4 downto 0) := (others=>'0');

	--Outputs
	SIGNAL rsd :  signed(31 downto 0);
	SIGNAL rtd :  signed(31 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: regfile PORT MAP(
		clk => clk,
		reset => reset,
		en_wr => en_wr,
		en_r1 => en_r1,
		en_r2 => en_r2,
		wra => wra,
		wrd => wrd,
		rra1 => rra1,
		rra2 => rra2,
		rsd => rsd,
		rtd => rtd
	);
	
	reset <= '1','0' after 5 ns;
	wra <= "00001","00010" after 20 ns;
	wrd <= X"00000001",X"00000002" after 20 ns;
	en_wr <='1','0' after 30 ns;
	rra1 <= "01001","00001" after 10 ns;
	en_r1 <='1';
	rra2 <= "00010";
	en_r2 <= '1';
	
	PROCESS
	BEGIN
		clk <='0';
		loop 
			clk <='1','0' after 5 ns;
			wait for 10 ns;
		end loop;
	END PROCESS;

END behavior;