muxalu1.vhd

32位微处理器的设计

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    22:39:29 12/17/2007 
-- Design Name: 
-- Module Name:    muxalu1 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use IEEE.std_logic_signed.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity muxalu1 is
    Port ( muxalu1_c : in  STD_LOGIC;
           muxalu1_rs : in  signed (31 downto 0);
           muxalu1_rt : in  signed (31 downto 0);
           muxalu1_out : out  signed (31 downto 0));
end muxalu1;

architecture Behavioral of muxalu1 is

begin
	process(muxalu1_rs,muxalu1_rt,muxalu1_c)
	begin
		case muxalu1_c is
			when '0' =>
				muxalu1_out <= muxalu1_rs;
			when '1' =>
				muxalu1_out <= muxalu1_rt;
			when others =>
				null;
		end case;
	end process;

end Behavioral;