pcalu.vhd

32位微处理器的设计

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    22:29:38 12/16/2007 
-- Design Name: 
-- Module Name:    pcalu - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use IEEE.std_logic_signed.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pcalu is
    Port ( pcalu_c : in  signed (2 downto 0);
           pcalu_in1 : in  signed (31 downto 0);
           pcalu_in2 : in  signed (31 downto 0);
           comp_out : in  signed (1 downto 0);
           pcalu_out : out  signed (31 downto 0));
end pcalu;

architecture Behavioral of pcalu is

begin
	process(pcalu_c,pcalu_in1,pcalu_in2,comp_out)
		variable pcalu_reg : signed(31 downto 0);
	begin
		case pcalu_c is
			when "001" =>   --bne
				if (comp_out /= "00") then
					pcalu_out <= pcalu_in1 + (pcalu_in2 sll 2);
				else
					pcalu_out <= pcalu_in1;
				end if;
			when "010" | "110" =>  --j&jal
				pcalu_out <= pcalu_in1(31 downto 28) & pcalu_in2(25 downto 0) & "00";
			when "011" =>  --jr
				pcalu_out <= pcalu_in2;
			when "100" =>  --beq
				if (comp_out = "00") then
					pcalu_out <= pcalu_in1 + (pcalu_in2 sll 2);
				else
					pcalu_out <= pcalu_in1;
				end if;
			when "101" =>  --pc=pc+4
				pcalu_out <= pcalu_in1 + pcalu_in2;
			when others =>
				pcalu_out <= pcalu_in1;
		end case;
	end process;

end Behavioral;