ir.vhd

32位微处理器的设计

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    21:45:00 12/16/2007 
-- Design Name: 	指令寄存器模块
-- Module Name:    ir - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use IEEE.std_logic_signed.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ir is
    Port ( memout : in  signed (31 downto 0);
           clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           en_ir : in  STD_LOGIC;
           instr : out  signed (31 downto 0));
end ir;

architecture Behavioral of ir is

begin
	process(clk,rst)
	begin
		if (rst='1') then
			instr <= (others=>'0');
		elsif (en_ir='1') then
			if (rising_edge(clk)) then
				instr <= memout;
			end if;
		end if;
	end process;


end Behavioral;