test_ir_vhd.vhd

32位微处理器的设计

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-- Company: 
-- Engineer:
--
-- Create Date:   21:59:40 12/16/2007
-- Design Name:   ir
-- Module Name:   E:/ISEworkspace/RISC32/test_ir_vhd.vhd
-- Project Name:  RISC32
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: ir
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;
use IEEE.std_logic_signed.ALL;

ENTITY test_ir_vhd_vhd IS
END test_ir_vhd_vhd;

ARCHITECTURE behavior OF test_ir_vhd_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT ir
	PORT(
		memout : IN signed(31 downto 0);
		clk : IN std_logic;
		rst : IN std_logic;
		en_ir : IN std_logic;          
		instr : OUT signed(31 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL clk :  std_logic := '0';
	SIGNAL rst :  std_logic := '0';
	SIGNAL en_ir :  std_logic := '0';
	SIGNAL memout :  signed(31 downto 0) := (others=>'0');

	--Outputs
	SIGNAL instr :  signed(31 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: ir PORT MAP(
		memout => memout,
		clk => clk,
		rst => rst,
		en_ir => en_ir,
		instr => instr
	);
	
	en_ir <= '1';
	rst <= '1','0' after 5 ns;
	tb : PROCESS
	BEGIN
		clk <= '1';
		wait for 5 ns;
		clk <= '0';
		wait for 5 ns;
	END PROCESS;

	process(clk)
	begin
		if (rising_edge(clk)) then
			memout <= memout + 1;
		end if;
	end process;
END;