alu.vhd

32位微处理器的设计

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:35:01 12/16/2007 
-- Design Name:  算术逻辑单元模块
-- Module Name:    alu - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.ALL;
use IEEE.std_logic_signed.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity alu is
    Port ( alu_c : in  signed(1 downto 0);
           aluin1 : in  signed (31 downto 0);
           aluin2 : in  signed (31 downto 0);
           aluout : out  signed (31 downto 0));
end alu;

architecture Behavioral of alu is
	constant alunop:signed(1 downto 0):="00";    
	constant aluadd_addu_addiu_addi:signed(1 downto 0):="01"; --带符号加
	constant alusll:signed(1 downto 0):="11";   --左移自然数
	constant alusubu:signed(1 downto 0):="10";  --带符号减
begin
	process(alu_c,aluin1,aluin2)
	begin
		case alu_c is
			when aluadd_addu_addiu_addi =>
					aluout <= aluin1+aluin2;
			when alusll =>
					aluout <= aluin1 sll(to_integer(aluin2));
			when alusubu =>
					aluout <= aluin1-aluin2;
			when others =>
					null;
		end case;
	end process;
end Behavioral;