muxwrd.vhd

32位微处理器的设计

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    22:53:01 12/17/2007 
-- Design Name: 
-- Module Name:    muxwrd - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use IEEE.std_logic_signed.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity muxwrd is
    Port ( muxwrd_c : in  signed (2 downto 0);
           muxwrd_aluout : in  signed (31 downto 0);
           muxwrd_imm : in  signed (31 downto 0);
           muxwrd_pc : in  signed (31 downto 0);
           muxwrd_instr : in  signed (31 downto 0);
           muxwrd_out : out  signed (31 downto 0));
end muxwrd;

architecture Behavioral of muxwrd is

begin
	process(muxwrd_c,muxwrd_aluout,muxwrd_imm,muxwrd_pc,muxwrd_instr)
	begin
		case muxwrd_c is
			when "001" =>
				muxwrd_out <= muxwrd_aluout;
			when "010" =>
				muxwrd_out <= muxwrd_pc;
			when "011" =>
				muxwrd_out <= muxwrd_imm;
			when "100" =>
				muxwrd_out <= muxwrd_instr;
			when "101" =>
				muxwrd_out <= (0=>'1',others=>'0');
			when "110" =>
				muxwrd_out <= (others=>'0');
			when others =>
				null;
		end case;
	end process;


end Behavioral;