test_alu_vhd.vhd

32位微处理器的设计

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:58:38 12/16/2007 
-- Design Name:    算术逻辑单元模块的测试
-- Module Name:    test_alu_vhd - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use IEEE.std_logic_signed.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity test_alu_vhd is
end test_alu_vhd;

architecture Behavioral of test_alu_vhd is
   --元件声明
	component alu
    Port ( alu_c : in  signed(1 downto 0);
           aluin1 : in  signed (31 downto 0);
           aluin2 : in  signed (31 downto 0);
           aluout : out  signed (31 downto 0));
	end component;
	--输入信号
	signal alu_c:signed(1 downto 0):=(others=>'0');
	signal aluin1:signed(31 downto 0):=(others=>'0');
	signal aluin2:signed(31 downto 0):=(others=>'0');
	--输出信号
	signal aluout:signed(31 downto 0);
	
begin
	--初始化
	uut:alu 
			port map(alu_c => alu_c,
						aluin1 => aluin1,
						aluin2 => aluin2,
						aluout => aluout);
	--激励信号
	aluin1 <=X"00000007";
	aluin2 <=X"00000002";
	process
	begin
		alu_c<="00";
		WAIT FOR 10 ns;
		alu_c<="01";
		wait for 10 ns;
		alu_c<="10";
		wait for 10 ns;
		alu_c<="11";
		wait;
	end process;
			
end Behavioral;