t_mem_vhd.vhd

32位微处理器的设计

--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   09:31:38 12/21/2007
-- Design Name:   MEM
-- Module Name:   E:/ISEworkspace/RISC32/t_mem_vhd.vhd
-- Project Name:  RISC32
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: MEM
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_signed.all;
USE ieee.numeric_std.ALL;

ENTITY t_mem_vhd_vhd IS
END t_mem_vhd_vhd;

ARCHITECTURE behavior OF t_mem_vhd_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT MEM
	PORT(
		DI : IN signed(31 downto 0);
		A : IN signed(31 downto 0);
		clk : IN std_logic;
		reset : IN std_logic;
		Ww : IN std_logic;
		Wb : IN std_logic;
		R : IN std_logic;          
		DO : OUT signed(31 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL clk :  std_logic := '0';
	SIGNAL reset :  std_logic := '0';
	SIGNAL Ww :  std_logic := '0';
	SIGNAL Wb :  std_logic := '0';
	SIGNAL R :  std_logic := '0';
	SIGNAL DI :  signed(31 downto 0) := (others=>'0');
	SIGNAL A :  signed(31 downto 0) := (others=>'0');

	--Outputs
	SIGNAL DO :  signed(31 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: MEM PORT MAP(
		DI => DI,
		DO => DO,
		A => A,
		clk => clk,
		reset => reset,
		Ww => Ww,
		Wb => Wb,
		R => R
	);
	
	--ji li xin  hao
	
	DI<=(OTHERS=>'1');
	A<=(17=>'1',2=>'1',OTHERS=>'0');
	Reset<='1','0' after 5 ns;
   R<='1','0' AFTER 20 ns,'1'	after 40 ns,'0' after 50 ns,'1' after 60 ns;
	Wb<='0','1' after 30 ns,'0' after 40 ns;
	Ww<='0','1' after 50 ns,'0' after 60 ns;

	PROCESS
	BEGIN


      clk<='0';
		
		loop 
		clk<='1','0' after 5 ns;
		wait for 10 ns;
		end loop;
		-- Wait 100 ns for global reset to finish
		wait for 100 ns;

		-- Place stimulus here

		wait; -- will wait forever
	END PROCESS;

END  behavior;