muxpcalu.vhd

32位微处理器的设计

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    22:49:13 12/17/2007 
-- Design Name: 
-- Module Name:    muxpcalu - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use IEEE.std_logic_signed.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity muxpcalu is
    Port ( muxpcalu_c : in  signed (1 downto 0);
           muxpcalu_imm : in  signed (31 downto 0);
           muxpcalu_rs : in  signed (31 downto 0);
           muxpcalu_out : out  signed (31 downto 0));
end muxpcalu;

architecture Behavioral of muxpcalu is

begin
	process(muxpcalu_c,muxpcalu_imm,muxpcalu_rs)
	begin
		case muxpcalu_c is 
			when "01" =>
				muxpcalu_out <= muxpcalu_imm;
			when "10" =>
				muxpcalu_out <= muxpcalu_rs;
			when others =>
				muxpcalu_out <= (2=>'1',others=>'0');
		end case;
	end process;

end Behavioral;