comparer.vhd

32位微处理器的设计

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:49:10 12/16/2007 
-- Design Name:    比较器模块
-- Module Name:    comparer - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use IEEE.std_logic_signed.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity comparer is
	port( en_comp:IN std_logic;
			comp_in1:IN signed(31 downto 0);
			comp_in2:IN signed(31 downto 0);
			comp_out:OUT signed(1 downto 0));
end comparer;

architecture Behavioral of comparer is
--如果compin1大于compin2 输出01 
--如果compin1小于compin2 输出10
--如果compin1等于compin2 输出00

begin
	process(comp_in1,comp_in2,en_comp)
		variable x:signed(31 downto 0);
	begin
		if (en_comp='1') then
			x:=comp_in1 - comp_in2;
			if (x=X"0000000000") then
				comp_out <= "00";
			elsif (x(31)='0') then
				comp_out <= "01";
			elsif (x(31)='1') then
				comp_out <= "10";
			end if;
		end if;
	end process;

end Behavioral;