regfile.vhd

32位微处理器的设计

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    08:56:40 12/17/2007 
-- Design Name:   通用寄存器组模块
-- Module Name:    regfile - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use IEEE.std_logic_signed.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity regfile is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           en_wr : in  STD_LOGIC;
           en_r1 : in  STD_LOGIC;
           en_r2 : in  STD_LOGIC;
           wra : in  signed (4 downto 0);
           wrd : in  signed (31 downto 0);
           rra1 : in  signed (4 downto 0);
           rra2 : in  signed (4 downto 0);
           rsd : out  signed (31 downto 0);
           rtd : out  signed (31 downto 0));
end regfile;

architecture Behavioral of regfile is
	type array2 is array(31 downto 0) of signed(31 downto 0);
	signal regf:array2;
begin
	process(reset,clk)
	begin
		--reset
		if (reset='1') then
			regf <= (others => (others => '0'));
			regf(9) <= X"8001fff0";
		else
			--read port 1
			if (en_r1='1') then
				rsd <= regf(to_integer(unsigned(rra1)));
			end if;
			--read port 2
			if (en_r2='1') then
				rtd <= regf(to_integer(unsigned(rra2)));
			end if;
			--write port
			if (rising_edge(clk) and en_wr = '1') then
				regf(to_integer(unsigned(wra))) <= wrd;
			end if;
		end if;
	end process;

end Behavioral;