test_pcalu_vhd.vhd

32位微处理器的设计

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-- Company: 
-- Engineer:
--
-- Create Date:   22:51:13 12/16/2007
-- Design Name:   pcalu
-- Module Name:   E:/ISEworkspace/RISC32/test_pcalu_vhd.vhd
-- Project Name:  RISC32
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: pcalu
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;
use IEEE.std_logic_signed.ALL;

ENTITY test_pcalu_vhd_vhd IS
END test_pcalu_vhd_vhd;

ARCHITECTURE behavior OF test_pcalu_vhd_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT pcalu
	PORT(
		pcalu_c : IN signed(2 downto 0);
		pcalu_in1 : IN signed(31 downto 0);
		pcalu_in2 : IN signed(31 downto 0);
		comp_out : IN signed(1 downto 0);          
		pcalu_out : OUT signed(31 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL pcalu_c :  signed(2 downto 0) := (others=>'0');
	SIGNAL pcalu_in1 :  signed(31 downto 0) := (others=>'0');
	SIGNAL pcalu_in2 :  signed(31 downto 0) := (others=>'0');
	SIGNAL comp_out :  signed(1 downto 0) := (others=>'0');
	signal clk      : std_logic;

	--Outputs
	SIGNAL pcalu_out :  signed(31 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: pcalu PORT MAP(
		pcalu_c => pcalu_c,
		pcalu_in1 => pcalu_in1,
		pcalu_in2 => pcalu_in2,
		comp_out => comp_out,
		pcalu_out => pcalu_out
	);

	pcalu_in1 <= X"00000007";
	pcalu_in2 <= X"00000002";
	comp_out <= "10";
	
	t1 : PROCESS(clk)
	BEGIN
		if (rising_edge(clk)) then
			pcalu_c <= pcalu_c + 1;
		end if;
	end process;

	t2 :process
	begin
		clk <= '0';
		loop
			clk <='1','0' after 5 ns;
			wait for 10 ns;
		end loop;
	END PROCESS;

END;