📄 prev_cmp_light.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 10 17:51:09 2008 " "Info: Processing started: Sat May 10 17:51:09 2008" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off light -c light " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off light -c light" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "124 " "Info: Allocated 124 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat May 10 17:51:19 2008 " "Info: Processing ended: Sat May 10 17:51:19 2008" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 10 17:51:21 2008 " "Info: Processing started: Sat May 10 17:51:21 2008" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off light -c light --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off light -c light --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 8 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "cout " "Info: Detected ripple clock \"cout\" as buffer" { } { { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 15 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "cout" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register counter\[10\] register counter\[16\] 195.73 MHz 5.109 ns Internal " "Info: Clock \"clk\" has Internal fmax of 195.73 MHz between source register \"counter\[10\]\" and destination register \"counter\[16\]\" (period= 5.109 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.848 ns + Longest register register " "Info: + Longest register to register delay is 4.848 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter\[10\] 1 REG LC_X10_Y2_N5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y2_N5; Fanout = 4; REG Node = 'counter\[10\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { counter[10] } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.264 ns) + CELL(0.442 ns) 1.706 ns Equal0~259 2 COMB LC_X9_Y3_N2 1 " "Info: 2: + IC(1.264 ns) + CELL(0.442 ns) = 1.706 ns; Loc. = LC_X9_Y3_N2; Fanout = 1; COMB Node = 'Equal0~259'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.706 ns" { counter[10] Equal0~259 } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.168 ns) + CELL(0.114 ns) 2.988 ns Equal0~261 3 COMB LC_X10_Y1_N3 2 " "Info: 3: + IC(1.168 ns) + CELL(0.114 ns) = 2.988 ns; Loc. = LC_X10_Y1_N3; Fanout = 2; COMB Node = 'Equal0~261'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.282 ns" { Equal0~259 Equal0~261 } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 3.284 ns Equal0~264 4 COMB LC_X10_Y1_N4 8 " "Info: 4: + IC(0.182 ns) + CELL(0.114 ns) = 3.284 ns; Loc. = LC_X10_Y1_N4; Fanout = 8; COMB Node = 'Equal0~264'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { Equal0~261 Equal0~264 } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.255 ns) + CELL(0.309 ns) 4.848 ns counter\[16\] 5 REG LC_X10_Y2_N1 3 " "Info: 5: + IC(1.255 ns) + CELL(0.309 ns) = 4.848 ns; Loc. = LC_X10_Y2_N1; Fanout = 3; REG Node = 'counter\[16\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.564 ns" { Equal0~264 counter[16] } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.979 ns ( 20.19 % ) " "Info: Total cell delay = 0.979 ns ( 20.19 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.869 ns ( 79.81 % ) " "Info: Total interconnect delay = 3.869 ns ( 79.81 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.848 ns" { counter[10] Equal0~259 Equal0~261 Equal0~264 counter[16] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.848 ns" { counter[10] Equal0~259 Equal0~261 Equal0~264 counter[16] } { 0.000ns 1.264ns 1.168ns 0.182ns 1.255ns } { 0.000ns 0.442ns 0.114ns 0.114ns 0.309ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.730 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 26 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 26; CLK Node = 'clk'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns counter\[16\] 2 REG LC_X10_Y2_N1 3 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X10_Y2_N1; Fanout = 3; REG Node = 'counter\[16\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.261 ns" { clk counter[16] } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.85 % ) " "Info: Total cell delay = 2.180 ns ( 79.85 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns ( 20.15 % ) " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.730 ns" { clk counter[16] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 counter[16] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.730 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 26 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 26; CLK Node = 'clk'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns counter\[10\] 2 REG LC_X10_Y2_N5 4 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X10_Y2_N5; Fanout = 4; REG Node = 'counter\[10\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.261 ns" { clk counter[10] } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.85 % ) " "Info: Total cell delay = 2.180 ns ( 79.85 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns ( 20.15 % ) " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.730 ns" { clk counter[10] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 counter[10] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.730 ns" { clk counter[16] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 counter[16] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.730 ns" { clk counter[10] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 counter[10] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 20 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 20 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.848 ns" { counter[10] Equal0~259 Equal0~261 Equal0~264 counter[16] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.848 ns" { counter[10] Equal0~259 Equal0~261 Equal0~264 counter[16] } { 0.000ns 1.264ns 1.168ns 0.182ns 1.255ns } { 0.000ns 0.442ns 0.114ns 0.114ns 0.309ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.730 ns" { clk counter[16] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 counter[16] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.730 ns" { clk counter[10] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 counter[10] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "temp2\[1\] left_in clk 0.534 ns register " "Info: tsu for register \"temp2\[1\]\" (data pin = \"left_in\", clock pin = \"clk\") is 0.534 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.916 ns + Longest pin register " "Info: + Longest pin to register delay is 8.916 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns left_in 1 PIN PIN_32 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_32; Fanout = 4; PIN Node = 'left_in'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { left_in } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.113 ns) + CELL(0.590 ns) 8.172 ns temp2~324 2 COMB LC_X5_Y10_N3 2 " "Info: 2: + IC(6.113 ns) + CELL(0.590 ns) = 8.172 ns; Loc. = LC_X5_Y10_N3; Fanout = 2; COMB Node = 'temp2~324'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.703 ns" { left_in temp2~324 } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 32 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.435 ns) + CELL(0.309 ns) 8.916 ns temp2\[1\] 3 REG LC_X5_Y10_N6 6 " "Info: 3: + IC(0.435 ns) + CELL(0.309 ns) = 8.916 ns; Loc. = LC_X5_Y10_N6; Fanout = 6; REG Node = 'temp2\[1\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.744 ns" { temp2~324 temp2[1] } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.368 ns ( 26.56 % ) " "Info: Total cell delay = 2.368 ns ( 26.56 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.548 ns ( 73.44 % ) " "Info: Total interconnect delay = 6.548 ns ( 73.44 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.916 ns" { left_in temp2~324 temp2[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.916 ns" { left_in left_in~out0 temp2~324 temp2[1] } { 0.000ns 0.000ns 6.113ns 0.435ns } { 0.000ns 1.469ns 0.590ns 0.309ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 34 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.419 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 8.419 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 26 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 26; CLK Node = 'clk'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.935 ns) 2.954 ns cout 2 REG LC_X10_Y1_N4 7 " "Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X10_Y1_N4; Fanout = 7; REG Node = 'cout'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk cout } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.754 ns) + CELL(0.711 ns) 8.419 ns temp2\[1\] 3 REG LC_X5_Y10_N6 6 " "Info: 3: + IC(4.754 ns) + CELL(0.711 ns) = 8.419 ns; Loc. = LC_X5_Y10_N6; Fanout = 6; REG Node = 'temp2\[1\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.465 ns" { cout temp2[1] } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 37.00 % ) " "Info: Total cell delay = 3.115 ns ( 37.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.304 ns ( 63.00 % ) " "Info: Total interconnect delay = 5.304 ns ( 63.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.419 ns" { clk cout temp2[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.419 ns" { clk clk~out0 cout temp2[1] } { 0.000ns 0.000ns 0.550ns 4.754ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.916 ns" { left_in temp2~324 temp2[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.916 ns" { left_in left_in~out0 temp2~324 temp2[1] } { 0.000ns 0.000ns 6.113ns 0.435ns } { 0.000ns 1.469ns 0.590ns 0.309ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.419 ns" { clk cout temp2[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.419 ns" { clk clk~out0 cout temp2[1] } { 0.000ns 0.000ns 0.550ns 4.754ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk voice voice~reg0 13.245 ns register " "Info: tco from clock \"clk\" to destination pin \"voice\" through register \"voice~reg0\" is 13.245 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.419 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.419 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 26 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 26; CLK Node = 'clk'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.935 ns) 2.954 ns cout 2 REG LC_X10_Y1_N4 7 " "Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X10_Y1_N4; Fanout = 7; REG Node = 'cout'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk cout } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.754 ns) + CELL(0.711 ns) 8.419 ns voice~reg0 3 REG LC_X5_Y10_N8 1 " "Info: 3: + IC(4.754 ns) + CELL(0.711 ns) = 8.419 ns; Loc. = LC_X5_Y10_N8; Fanout = 1; REG Node = 'voice~reg0'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.465 ns" { cout voice~reg0 } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 34 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 37.00 % ) " "Info: Total cell delay = 3.115 ns ( 37.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.304 ns ( 63.00 % ) " "Info: Total interconnect delay = 5.304 ns ( 63.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.419 ns" { clk cout voice~reg0 } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.419 ns" { clk clk~out0 cout voice~reg0 } { 0.000ns 0.000ns 0.550ns 4.754ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 34 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.602 ns + Longest register pin " "Info: + Longest register to pin delay is 4.602 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns voice~reg0 1 REG LC_X5_Y10_N8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y10_N8; Fanout = 1; REG Node = 'voice~reg0'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { voice~reg0 } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 34 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.478 ns) + CELL(2.124 ns) 4.602 ns voice 2 PIN PIN_36 0 " "Info: 2: + IC(2.478 ns) + CELL(2.124 ns) = 4.602 ns; Loc. = PIN_36; Fanout = 0; PIN Node = 'voice'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.602 ns" { voice~reg0 voice } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 46.15 % ) " "Info: Total cell delay = 2.124 ns ( 46.15 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.478 ns ( 53.85 % ) " "Info: Total interconnect delay = 2.478 ns ( 53.85 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.602 ns" { voice~reg0 voice } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.602 ns" { voice~reg0 voice } { 0.000ns 2.478ns } { 0.000ns 2.124ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.419 ns" { clk cout voice~reg0 } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.419 ns" { clk clk~out0 cout voice~reg0 } { 0.000ns 0.000ns 0.550ns 4.754ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.602 ns" { voice~reg0 voice } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.602 ns" { voice~reg0 voice } { 0.000ns 2.478ns } { 0.000ns 2.124ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "temp1\[1\] danger_in clk 0.861 ns register " "Info: th for register \"temp1\[1\]\" (data pin = \"danger_in\", clock pin = \"clk\") is 0.861 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.419 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 8.419 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 26 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 26; CLK Node = 'clk'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.935 ns) 2.954 ns cout 2 REG LC_X10_Y1_N4 7 " "Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X10_Y1_N4; Fanout = 7; REG Node = 'cout'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk cout } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.754 ns) + CELL(0.711 ns) 8.419 ns temp1\[1\] 3 REG LC_X4_Y10_N5 6 " "Info: 3: + IC(4.754 ns) + CELL(0.711 ns) = 8.419 ns; Loc. = LC_X4_Y10_N5; Fanout = 6; REG Node = 'temp1\[1\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.465 ns" { cout temp1[1] } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 37.00 % ) " "Info: Total cell delay = 3.115 ns ( 37.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.304 ns ( 63.00 % ) " "Info: Total interconnect delay = 5.304 ns ( 63.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.419 ns" { clk cout temp1[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.419 ns" { clk clk~out0 cout temp1[1] } { 0.000ns 0.000ns 0.550ns 4.754ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" { } { { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 34 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.573 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.573 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns danger_in 1 PIN PIN_28 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 8; PIN Node = 'danger_in'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { danger_in } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.626 ns) + CELL(0.478 ns) 7.573 ns temp1\[1\] 2 REG LC_X4_Y10_N5 6 " "Info: 2: + IC(5.626 ns) + CELL(0.478 ns) = 7.573 ns; Loc. = LC_X4_Y10_N5; Fanout = 6; REG Node = 'temp1\[1\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.104 ns" { danger_in temp1[1] } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.947 ns ( 25.71 % ) " "Info: Total cell delay = 1.947 ns ( 25.71 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.626 ns ( 74.29 % ) " "Info: Total interconnect delay = 5.626 ns ( 74.29 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.573 ns" { danger_in temp1[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.573 ns" { danger_in danger_in~out0 temp1[1] } { 0.000ns 0.000ns 5.626ns } { 0.000ns 1.469ns 0.478ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.419 ns" { clk cout temp1[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.419 ns" { clk clk~out0 cout temp1[1] } { 0.000ns 0.000ns 0.550ns 4.754ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.573 ns" { danger_in temp1[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.573 ns" { danger_in danger_in~out0 temp1[1] } { 0.000ns 0.000ns 5.626ns } { 0.000ns 1.469ns 0.478ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "106 " "Info: Allocated 106 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat May 10 17:51:23 2008 " "Info: Processing ended: Sat May 10 17:51:23 2008" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 3 s " "Info: Quartus II Full Compilation was successful. 0 errors, 3 warnings" { } { } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
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