prev_cmp_light.tan.qmsg

利用Altera公司FPGA芯片

{ "Info" "ITDB_TH_RESULT" "voice~reg0 danger_in clk 0.951 ns register " "Info: th for register \"voice~reg0\" (data pin = \"danger_in\", clock pin = \"clk\") is 0.951 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.874 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.874 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.935 ns) 2.954 ns cout 2 REG LC_X7_Y4_N4 7 " "Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X7_Y4_N4; Fanout = 7; REG Node = 'cout'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk cout } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.209 ns) + CELL(0.711 ns) 7.874 ns voice~reg0 3 REG LC_X1_Y2_N8 1 " "Info: 3: + IC(4.209 ns) + CELL(0.711 ns) = 7.874 ns; Loc. = LC_X1_Y2_N8; Fanout = 1; REG Node = 'voice~reg0'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.920 ns" { cout voice~reg0 } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 34 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 39.56 % ) " "Info: Total cell delay = 3.115 ns ( 39.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.759 ns ( 60.44 % ) " "Info: Total interconnect delay = 4.759 ns ( 60.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.874 ns" { clk cout voice~reg0 } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.874 ns" { clk clk~out0 cout voice~reg0 } { 0.000ns 0.000ns 0.550ns 4.209ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 34 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.938 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.938 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns danger_in 1 PIN PIN_28 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 8; PIN Node = 'danger_in'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { danger_in } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.160 ns) + CELL(0.309 ns) 6.938 ns voice~reg0 2 REG LC_X1_Y2_N8 1 " "Info: 2: + IC(5.160 ns) + CELL(0.309 ns) = 6.938 ns; Loc. = LC_X1_Y2_N8; Fanout = 1; REG Node = 'voice~reg0'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.469 ns" { danger_in voice~reg0 } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 34 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.778 ns ( 25.63 % ) " "Info: Total cell delay = 1.778 ns ( 25.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.160 ns ( 74.37 % ) " "Info: Total interconnect delay = 5.160 ns ( 74.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.938 ns" { danger_in voice~reg0 } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.938 ns" { danger_in danger_in~out0 voice~reg0 } { 0.000ns 0.000ns 5.160ns } { 0.000ns 1.469ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.874 ns" { clk cout voice~reg0 } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.874 ns" { clk clk~out0 cout voice~reg0 } { 0.000ns 0.000ns 0.550ns 4.209ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.938 ns" { danger_in voice~reg0 } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.938 ns" { danger_in danger_in~out0 voice~reg0 } { 0.000ns 0.000ns 5.160ns } { 0.000ns 1.469ns 0.309ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "106 " "Info: Allocated 106 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat May 10 17:57:06 2008 " "Info: Processing ended: Sat May 10 17:57:06 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}