prev_cmp_light.tan.qmsg

利用Altera公司FPGA芯片

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "cout " "Info: Detected ripple clock \"cout\" as buffer" {  } { { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 15 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "cout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register temp2\[1\] register temp2\[1\] 206.91 MHz 4.833 ns Internal " "Info: Clock \"clk\" has Internal fmax of 206.91 MHz between source register \"temp2\[1\]\" and destination register \"temp2\[1\]\" (period= 4.833 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.572 ns + Longest register register " "Info: + Longest register to register delay is 4.572 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns temp2\[1\] 1 REG LC_X1_Y2_N9 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y2_N9; Fanout = 6; REG Node = 'temp2\[1\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { temp2[1] } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.279 ns) + CELL(0.442 ns) 1.721 ns process1~57 2 COMB LC_X1_Y3_N7 1 " "Info: 2: + IC(1.279 ns) + CELL(0.442 ns) = 1.721 ns; Loc. = LC_X1_Y3_N7; Fanout = 1; COMB Node = 'process1~57'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.721 ns" { temp2[1] process1~57 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.454 ns) + CELL(0.292 ns) 2.467 ns process1~2 3 COMB LC_X1_Y3_N8 2 " "Info: 3: + IC(0.454 ns) + CELL(0.292 ns) = 2.467 ns; Loc. = LC_X1_Y3_N8; Fanout = 2; COMB Node = 'process1~2'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.746 ns" { process1~57 process1~2 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 2.763 ns temp2~323 4 COMB LC_X1_Y3_N9 4 " "Info: 4: + IC(0.182 ns) + CELL(0.114 ns) = 2.763 ns; Loc. = LC_X1_Y3_N9; Fanout = 4; COMB Node = 'temp2~323'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { process1~2 temp2~323 } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.202 ns) + CELL(0.607 ns) 4.572 ns temp2\[1\] 5 REG LC_X1_Y2_N9 6 " "Info: 5: + IC(1.202 ns) + CELL(0.607 ns) = 4.572 ns; Loc. = LC_X1_Y2_N9; Fanout = 6; REG Node = 'temp2\[1\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.809 ns" { temp2~323 temp2[1] } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.455 ns ( 31.82 % ) " "Info: Total cell delay = 1.455 ns ( 31.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.117 ns ( 68.18 % ) " "Info: Total interconnect delay = 3.117 ns ( 68.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.572 ns" { temp2[1] process1~57 process1~2 temp2~323 temp2[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.572 ns" { temp2[1] process1~57 process1~2 temp2~323 temp2[1] } { 0.000ns 1.279ns 0.454ns 0.182ns 1.202ns } { 0.000ns 0.442ns 0.292ns 0.114ns 0.607ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.874 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 7.874 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.935 ns) 2.954 ns cout 2 REG LC_X7_Y4_N4 7 " "Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X7_Y4_N4; Fanout = 7; REG Node = 'cout'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk cout } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.209 ns) + CELL(0.711 ns) 7.874 ns temp2\[1\] 3 REG LC_X1_Y2_N9 6 " "Info: 3: + IC(4.209 ns) + CELL(0.711 ns) = 7.874 ns; Loc. = LC_X1_Y2_N9; Fanout = 6; REG Node = 'temp2\[1\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.920 ns" { cout temp2[1] } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 39.56 % ) " "Info: Total cell delay = 3.115 ns ( 39.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.759 ns ( 60.44 % ) " "Info: Total interconnect delay = 4.759 ns ( 60.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.874 ns" { clk cout temp2[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.874 ns" { clk clk~out0 cout temp2[1] } { 0.000ns 0.000ns 0.550ns 4.209ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.874 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.874 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.935 ns) 2.954 ns cout 2 REG LC_X7_Y4_N4 7 " "Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X7_Y4_N4; Fanout = 7; REG Node = 'cout'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk cout } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.209 ns) + CELL(0.711 ns) 7.874 ns temp2\[1\] 3 REG LC_X1_Y2_N9 6 " "Info: 3: + IC(4.209 ns) + CELL(0.711 ns) = 7.874 ns; Loc. = LC_X1_Y2_N9; Fanout = 6; REG Node = 'temp2\[1\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.920 ns" { cout temp2[1] } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 39.56 % ) " "Info: Total cell delay = 3.115 ns ( 39.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.759 ns ( 60.44 % ) " "Info: Total interconnect delay = 4.759 ns ( 60.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.874 ns" { clk cout temp2[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.874 ns" { clk clk~out0 cout temp2[1] } { 0.000ns 0.000ns 0.550ns 4.209ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.874 ns" { clk cout temp2[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.874 ns" { clk clk~out0 cout temp2[1] } { 0.000ns 0.000ns 0.550ns 4.209ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.874 ns" { clk cout temp2[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.874 ns" { clk clk~out0 cout temp2[1] } { 0.000ns 0.000ns 0.550ns 4.209ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.572 ns" { temp2[1] process1~57 process1~2 temp2~323 temp2[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.572 ns" { temp2[1] process1~57 process1~2 temp2~323 temp2[1] } { 0.000ns 1.279ns 0.454ns 0.182ns 1.202ns } { 0.000ns 0.442ns 0.292ns 0.114ns 0.607ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.874 ns" { clk cout temp2[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.874 ns" { clk clk~out0 cout temp2[1] } { 0.000ns 0.000ns 0.550ns 4.209ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.874 ns" { clk cout temp2[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.874 ns" { clk clk~out0 cout temp2[1] } { 0.000ns 0.000ns 0.550ns 4.209ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "temp2\[1\] danger_in clk 1.038 ns register " "Info: tsu for register \"temp2\[1\]\" (data pin = \"danger_in\", clock pin = \"clk\") is 1.038 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.875 ns + Longest pin register " "Info: + Longest pin to register delay is 8.875 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns danger_in 1 PIN PIN_28 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 8; PIN Node = 'danger_in'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { danger_in } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.155 ns) + CELL(0.442 ns) 7.066 ns temp2~323 2 COMB LC_X1_Y3_N9 4 " "Info: 2: + IC(5.155 ns) + CELL(0.442 ns) = 7.066 ns; Loc. = LC_X1_Y3_N9; Fanout = 4; COMB Node = 'temp2~323'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.597 ns" { danger_in temp2~323 } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.202 ns) + CELL(0.607 ns) 8.875 ns temp2\[1\] 3 REG LC_X1_Y2_N9 6 " "Info: 3: + IC(1.202 ns) + CELL(0.607 ns) = 8.875 ns; Loc. = LC_X1_Y2_N9; Fanout = 6; REG Node = 'temp2\[1\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.809 ns" { temp2~323 temp2[1] } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.518 ns ( 28.37 % ) " "Info: Total cell delay = 2.518 ns ( 28.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.357 ns ( 71.63 % ) " "Info: Total interconnect delay = 6.357 ns ( 71.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.875 ns" { danger_in temp2~323 temp2[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.875 ns" { danger_in danger_in~out0 temp2~323 temp2[1] } { 0.000ns 0.000ns 5.155ns 1.202ns } { 0.000ns 1.469ns 0.442ns 0.607ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.874 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 7.874 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.935 ns) 2.954 ns cout 2 REG LC_X7_Y4_N4 7 " "Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X7_Y4_N4; Fanout = 7; REG Node = 'cout'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk cout } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.209 ns) + CELL(0.711 ns) 7.874 ns temp2\[1\] 3 REG LC_X1_Y2_N9 6 " "Info: 3: + IC(4.209 ns) + CELL(0.711 ns) = 7.874 ns; Loc. = LC_X1_Y2_N9; Fanout = 6; REG Node = 'temp2\[1\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.920 ns" { cout temp2[1] } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 39.56 % ) " "Info: Total cell delay = 3.115 ns ( 39.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.759 ns ( 60.44 % ) " "Info: Total interconnect delay = 4.759 ns ( 60.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.874 ns" { clk cout temp2[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.874 ns" { clk clk~out0 cout temp2[1] } { 0.000ns 0.000ns 0.550ns 4.209ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.875 ns" { danger_in temp2~323 temp2[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.875 ns" { danger_in danger_in~out0 temp2~323 temp2[1] } { 0.000ns 0.000ns 5.155ns 1.202ns } { 0.000ns 1.469ns 0.442ns 0.607ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.874 ns" { clk cout temp2[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.874 ns" { clk clk~out0 cout temp2[1] } { 0.000ns 0.000ns 0.550ns 4.209ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk right_out\[2\] temp2\[2\] 12.858 ns register " "Info: tco from clock \"clk\" to destination pin \"right_out\[2\]\" through register \"temp2\[2\]\" is 12.858 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.874 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.874 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.935 ns) 2.954 ns cout 2 REG LC_X7_Y4_N4 7 " "Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X7_Y4_N4; Fanout = 7; REG Node = 'cout'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk cout } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.209 ns) + CELL(0.711 ns) 7.874 ns temp2\[2\] 3 REG LC_X1_Y2_N6 6 " "Info: 3: + IC(4.209 ns) + CELL(0.711 ns) = 7.874 ns; Loc. = LC_X1_Y2_N6; Fanout = 6; REG Node = 'temp2\[2\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.920 ns" { cout temp2[2] } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 39.56 % ) " "Info: Total cell delay = 3.115 ns ( 39.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.759 ns ( 60.44 % ) " "Info: Total interconnect delay = 4.759 ns ( 60.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.874 ns" { clk cout temp2[2] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.874 ns" { clk clk~out0 cout temp2[2] } { 0.000ns 0.000ns 0.550ns 4.209ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.760 ns + Longest register pin " "Info: + Longest register to pin delay is 4.760 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns temp2\[2\] 1 REG LC_X1_Y2_N6 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y2_N6; Fanout = 6; REG Node = 'temp2\[2\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { temp2[2] } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.636 ns) + CELL(2.124 ns) 4.760 ns right_out\[2\] 2 PIN PIN_7 0 " "Info: 2: + IC(2.636 ns) + CELL(2.124 ns) = 4.760 ns; Loc. = PIN_7; Fanout = 0; PIN Node = 'right_out\[2\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.760 ns" { temp2[2] right_out[2] } "NODE_NAME" } } { "light.vhd" "" { Text "D:/Myquartus/light/light.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 44.62 % ) " "Info: Total cell delay = 2.124 ns ( 44.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.636 ns ( 55.38 % ) " "Info: Total interconnect delay = 2.636 ns ( 55.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.760 ns" { temp2[2] right_out[2] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.760 ns" { temp2[2] right_out[2] } { 0.000ns 2.636ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.874 ns" { clk cout temp2[2] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.874 ns" { clk clk~out0 cout temp2[2] } { 0.000ns 0.000ns 0.550ns 4.209ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.760 ns" { temp2[2] right_out[2] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.760 ns" { temp2[2] right_out[2] } { 0.000ns 2.636ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}