light.hier_info

利用Altera公司FPGA芯片

|light
clk => counter[23].CLK
clk => counter[22].CLK
clk => counter[21].CLK
clk => counter[20].CLK
clk => counter[19].CLK
clk => counter[18].CLK
clk => counter[17].CLK
clk => counter[16].CLK
clk => counter[15].CLK
clk => counter[14].CLK
clk => counter[13].CLK
clk => counter[12].CLK
clk => counter[11].CLK
clk => counter[10].CLK
clk => counter[9].CLK
clk => counter[8].CLK
clk => counter[7].CLK
clk => counter[6].CLK
clk => counter[5].CLK
clk => counter[4].CLK
clk => counter[3].CLK
clk => counter[2].CLK
clk => counter[1].CLK
clk => counter[0].CLK
clk => cout.CLK
stop_in => temp1[2].PRESET
stop_in => temp1[1].PRESET
stop_in => temp1[0].PRESET
stop_in => temp2[2].PRESET
stop_in => temp2[1].PRESET
stop_in => temp2[0].PRESET
stop_in => voice~reg0.PRESET
danger_in => voice~0.OUTPUTSELECT
danger_in => temp2~16.OUTPUTSELECT
danger_in => temp2~15.OUTPUTSELECT
danger_in => temp2~14.OUTPUTSELECT
danger_in => temp1~13.OUTPUTSELECT
danger_in => temp1~12.OUTPUTSELECT
danger_in => temp1~11.OUTPUTSELECT
danger_in => voice~3.OUTPUTSELECT
left_in => temp2~13.OUTPUTSELECT
left_in => temp2~12.OUTPUTSELECT
left_in => temp2~11.OUTPUTSELECT
left_in => temp1~10.OUTPUTSELECT
left_in => temp1~9.OUTPUTSELECT
left_in => temp1~8.OUTPUTSELECT
left_in => voice~2.OUTPUTSELECT
right_in => temp2~10.OUTPUTSELECT
right_in => temp2~9.OUTPUTSELECT
right_in => temp2~8.OUTPUTSELECT
right_in => voice~1.OUTPUTSELECT
left_out[0] <= temp1[0].DB_MAX_OUTPUT_PORT_TYPE
left_out[1] <= temp1[1].DB_MAX_OUTPUT_PORT_TYPE
left_out[2] <= temp1[2].DB_MAX_OUTPUT_PORT_TYPE
right_out[0] <= temp2[0].DB_MAX_OUTPUT_PORT_TYPE
right_out[1] <= temp2[1].DB_MAX_OUTPUT_PORT_TYPE
right_out[2] <= temp2[2].DB_MAX_OUTPUT_PORT_TYPE
voice <= voice~reg0.DB_MAX_OUTPUT_PORT_TYPE