light.vhd.bak

利用Altera公司FPGA芯片

library ieee;
use ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
USE IEEE.STD_LOGIC_ARITH.ALL ;
entity light is
	port
	(
		clk,stop_in,danger_in,left_in,right_in : in  std_logic;
		left_out,right_out       	           : out std_logic_vector(2 downto 0);
	    voice                                  : out std_logic
	);
end light;

architecture behave of light is
    signal cout        : std_logic;
	signal counter     : integer range 0 to 9999999;
begin
    process(clk)
        begin
            if(clk'event and clk='1')then
                if(counter=9999999)then
                    counter<=0;
                    cout<='1';
                     else
                    counter<=counter+1; 
                    cout<='0';
                end if; 
            end if; 
    end process;

    process(stop_in,danger_in,cout,left_in,right_in)
    variable temp1,temp2 : std_logic_vector(2 downto 0);
        begin
            if(stop_in='0')then
                voice<='1';
                temp1:="111";
                temp2:="111"; 
            elsif(cout'event and cout='1')then
                    if(danger_in='0')then
							voice<='0';
							if ((temp1="000" and temp2="000")or(temp1="111" and temp2="111"))then
							 temp1:=not temp1;
							 temp2:=not temp2;
							else
							 temp1:="000";
							 temp2:="000";
							end if;
					elsif(left_in='0' )then
								if(danger_in='1')then
								voice<='1';
								end if;
								if(temp1="000" or temp1="111")then   
								   temp1:="001";
								else
								   temp1:=temp1(1 downto 0)&'0';
								   if(temp1="000")then
								      temp1:="001";
								   end if;
								end if;
								temp2:="000";
					elsif(right_in='0')then
								if(danger_in='1')then
									voice<='1';
								end if;
								if(temp2="000" or temp1="111")then
								temp2:="100";
								  else
									temp2:='0'&temp2(2 downto 1);
								    if(temp2="000")then
								       temp2:="100";
								    end if;
								end if;
								temp1:="000";
					else    
							voice<='1';
							temp1:="000";
							temp2:="000";
                    end if;
				
            end if;
        left_out<=temp1;
        right_out<=temp2;  
    end process;            
 end behave;