light.tan.rpt

利用Altera公司FPGA芯片

; N/A           ; None        ; 0.505 ns  ; right_in  ; temp2[0]   ; clk      ;
; N/A           ; None        ; 0.504 ns  ; right_in  ; temp2[1]   ; clk      ;
; N/A           ; None        ; 0.489 ns  ; left_in   ; temp1[1]   ; clk      ;
; N/A           ; None        ; 0.487 ns  ; left_in   ; temp1[2]   ; clk      ;
; N/A           ; None        ; 0.428 ns  ; left_in   ; temp2[2]   ; clk      ;
; N/A           ; None        ; 0.396 ns  ; danger_in ; temp2[0]   ; clk      ;
; N/A           ; None        ; 0.395 ns  ; danger_in ; temp2[1]   ; clk      ;
; N/A           ; None        ; 0.178 ns  ; left_in   ; temp2[0]   ; clk      ;
; N/A           ; None        ; 0.177 ns  ; left_in   ; temp2[1]   ; clk      ;
; N/A           ; None        ; -0.112 ns ; danger_in ; temp1[0]   ; clk      ;
; N/A           ; None        ; -0.528 ns ; left_in   ; temp1[0]   ; clk      ;
+---------------+-------------+-----------+-----------+------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Sat May 10 20:27:30 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off light -c light --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "cout" as buffer
Info: Clock "clk" has Internal fmax of 206.91 MHz between source register "temp2[1]" and destination register "temp2[1]" (period= 4.833 ns)
    Info: + Longest register to register delay is 4.572 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y2_N9; Fanout = 6; REG Node = 'temp2[1]'
        Info: 2: + IC(1.279 ns) + CELL(0.442 ns) = 1.721 ns; Loc. = LC_X1_Y3_N7; Fanout = 1; COMB Node = 'process1~57'
        Info: 3: + IC(0.454 ns) + CELL(0.292 ns) = 2.467 ns; Loc. = LC_X1_Y3_N8; Fanout = 2; COMB Node = 'process1~2'
        Info: 4: + IC(0.182 ns) + CELL(0.114 ns) = 2.763 ns; Loc. = LC_X1_Y3_N9; Fanout = 4; COMB Node = 'temp2~323'
        Info: 5: + IC(1.202 ns) + CELL(0.607 ns) = 4.572 ns; Loc. = LC_X1_Y2_N9; Fanout = 6; REG Node = 'temp2[1]'
        Info: Total cell delay = 1.455 ns ( 31.82 % )
        Info: Total interconnect delay = 3.117 ns ( 68.18 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 7.874 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 25; CLK Node = 'clk'
            Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X7_Y4_N4; Fanout = 7; REG Node = 'cout'
            Info: 3: + IC(4.209 ns) + CELL(0.711 ns) = 7.874 ns; Loc. = LC_X1_Y2_N9; Fanout = 6; REG Node = 'temp2[1]'
            Info: Total cell delay = 3.115 ns ( 39.56 % )
            Info: Total interconnect delay = 4.759 ns ( 60.44 % )
        Info: - Longest clock path from clock "clk" to source register is 7.874 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 25; CLK Node = 'clk'
            Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X7_Y4_N4; Fanout = 7; REG Node = 'cout'
            Info: 3: + IC(4.209 ns) + CELL(0.711 ns) = 7.874 ns; Loc. = LC_X1_Y2_N9; Fanout = 6; REG Node = 'temp2[1]'
            Info: Total cell delay = 3.115 ns ( 39.56 % )
            Info: Total interconnect delay = 4.759 ns ( 60.44 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "temp2[1]" (data pin = "danger_in", clock pin = "clk") is 1.038 ns
    Info: + Longest pin to register delay is 8.875 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 8; PIN Node = 'danger_in'
        Info: 2: + IC(5.155 ns) + CELL(0.442 ns) = 7.066 ns; Loc. = LC_X1_Y3_N9; Fanout = 4; COMB Node = 'temp2~323'
        Info: 3: + IC(1.202 ns) + CELL(0.607 ns) = 8.875 ns; Loc. = LC_X1_Y2_N9; Fanout = 6; REG Node = 'temp2[1]'
        Info: Total cell delay = 2.518 ns ( 28.37 % )
        Info: Total interconnect delay = 6.357 ns ( 71.63 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 7.874 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 25; CLK Node = 'clk'
        Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X7_Y4_N4; Fanout = 7; REG Node = 'cout'
        Info: 3: + IC(4.209 ns) + CELL(0.711 ns) = 7.874 ns; Loc. = LC_X1_Y2_N9; Fanout = 6; REG Node = 'temp2[1]'
        Info: Total cell delay = 3.115 ns ( 39.56 % )
        Info: Total interconnect delay = 4.759 ns ( 60.44 % )
Info: tco from clock "clk" to destination pin "right_out[2]" through register "temp2[2]" is 12.858 ns
    Info: + Longest clock path from clock "clk" to source register is 7.874 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 25; CLK Node = 'clk'
        Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X7_Y4_N4; Fanout = 7; REG Node = 'cout'
        Info: 3: + IC(4.209 ns) + CELL(0.711 ns) = 7.874 ns; Loc. = LC_X1_Y2_N6; Fanout = 6; REG Node = 'temp2[2]'
        Info: Total cell delay = 3.115 ns ( 39.56 % )
        Info: Total interconnect delay = 4.759 ns ( 60.44 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 4.760 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y2_N6; Fanout = 6; REG Node = 'temp2[2]'
        Info: 2: + IC(2.636 ns) + CELL(2.124 ns) = 4.760 ns; Loc. = PIN_7; Fanout = 0; PIN Node = 'right_out[2]'
        Info: Total cell delay = 2.124 ns ( 44.62 % )
        Info: Total interconnect delay = 2.636 ns ( 55.38 % )
Info: th for register "voice~reg0" (data pin = "danger_in", clock pin = "clk") is 0.951 ns
    Info: + Longest clock path from clock "clk" to destination register is 7.874 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 25; CLK Node = 'clk'
        Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X7_Y4_N4; Fanout = 7; REG Node = 'cout'
        Inf