sdh_clk.vhd

该程序是同步帧检测

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;


entity sdh_clk is
	 port(
		 clk_19m 		: in STD_LOGIC;
		 reset 			: in STD_LOGIC;
		 clk_10m 		: in STD_LOGIC;	 
		 ena_64k		: out STD_LOGIC;
		 ena_192k		: out STD_LOGIC;
--		 clk_64k 		: out STD_LOGIC;
--		 clk_192k 		: out STD_LOGIC;
		 ena_1250k 		: out STD_LOGIC
	     );
end sdh_clk;

--}} End of automatically maintained section

architecture clk_proc of sdh_clk is   
signal count1			: std_logic_vector(1 downto 0);	
signal count2			: std_logic_vector(8 downto 0);
signal count3			: std_logic_vector(2 downto 0);			 
signal f2				: std_logic;
begin												   
	process(clk_19m,reset)
	begin
		if reset='0' then			
			count1 <= (others => '0');
			count2 <= (others => '0');	   
			f2 <= '0';
			ena_192k <= '0';
			ena_64k <= '0';
		elsif clk_19m'event and clk_19m='1' then	
			ena_192k <= f2;	   
			if count2 >= "110010101" then
				count2 <= count2 - "110010001" ; 
				f2 <= '1' ;	
			else
				count2 <= count2 + "000000100";	  
				f2 <= '0';
			end if;	
			
			if f2='1' then		
				if count1 /= "10" then	  
					count1 <= count1 + "01";
				else	
					count1 <= "00";	   
				end if;				   
			end if;	 
			
			if count1 = "00" then			
				ena_64k <= f2;	  		 
			else			
				ena_64k <= '0';
			end if;	   
		end if;
	end process;
	
	process(clk_10m,reset)
	begin
		if reset='0' then
			count3 <= (others => '0');			 
			ena_1250k <= '0';
		elsif clk_10m'event and clk_10m='1' then
			count3 <= count3 + "001";	 
			ena_1250k <= (not count3(2)) and (not count3(1)) and (not count3(0));
		end if;
	end process;
				
			
										
			

	 -- enter your statements here --

end clk_proc;