sdh_top.vhd

该程序是同步帧检测

library IEEE;
use IEEE.STD_LOGIC_1164.all; 
use ieee.std_logic_unsigned.all;



entity sdh_transact_top is
	 port(
		 rc_clk 			: in STD_LOGIC;	--
		 reset 				: in STD_LOGIC;
		 clk_10m 			: in STD_LOGIC;
		 sdh_din 			: in STD_LOGIC_VECTOR(7 downto 0);
		 E1_out 			: out STD_LOGIC;
		 F1_out 			: out STD_LOGIC;
		 clk_64k 			: out STD_LOGIC;
		 DDC1_out			: out STD_LOGIC;
		 clk_192k 			: out STD_LOGIC;
		 sdh_cost_out 		: out STD_LOGIC;
		 sdh_cost_den 		: out STD_LOGIC;
		 clk_10m_out 		: out STD_LOGIC
	     );
end sdh_transact_top;

--}} End of automatically maintained section

architecture sdh_transact_top of sdh_transact_top is   
signal frame_state 					: std_logic_vector(2 downto 0);
signal line_cnt 					: std_logic_vector(8 downto 0);
signal column_cnt 					: std_logic_vector(3 downto 0);
signal f1_temp,sdh_out_temp			: std_logic_vector(7 downto 0);	 
signal e1_temp1,e1_temp2,e1_temp3	: std_logic_vector(7 downto 0);
signal ddc1_temp					: std_logic_vector(23 downto 0);
signal fifo_waddr,fifo_raddr		: std_logic_vector(5 downto 0);
signal fifo_wren, fifo_rden			: std_logic;   
signal ena_64k,ena_192k,ena_1250k	: std_logic;  
signal ef_ena,ddc1_ena				: std_logic;	  
signal ena_1250k_delay				: std_logic; 
signal ena_192k_delay,ena_64k_delay : std_logic;
signal index_ef,index_sdh			: integer range 0 to 7;	   
signal index_ddc1					: integer range 0 to 23;   
signal sdh_cost_cnt 				: integer range 0 to 71;
signal synchro_flag,fifo_rd_start	: std_logic;   
signal fifo_rd_start_delay			: std_logic;
signal sdh_data_delay				: std_logic_vector(7 downto 0);


	component clk_proc 
		port(
			 clk_19m 		: in STD_LOGIC;
			 reset 			: in STD_LOGIC;
			 clk_10m 		: in STD_LOGIC;	
			 ena_64k		: out STD_LOGIC;
			 ena_192k		: out STD_LOGIC;
			 ena_1250k 		: out STD_LOGIC
		     );
	end component clk_proc;	   
	
	component blockdram 
	generic( 
		depth:	integer;
		Dwidth: integer;
		Awidth:	integer
		);
	port(
		addra: IN std_logic_VECTOR(Awidth-1 downto 0);
		clka: IN std_logic;
		addrb: IN std_logic_VECTOR(Awidth-1 downto 0);
		clkb: IN std_logic;
		dia: IN std_logic_VECTOR(Dwidth-1 downto 0);
		wea: IN std_logic;	 
		rea: IN std_logic;
		dob: OUT std_logic_VECTOR(Dwidth-1 downto 0));
	end component blockdram;	
--	port(
--	addra: IN std_logic_VECTOR(5 downto 0);
--	clka: IN std_logic;
--	addrb: IN std_logic_VECTOR(5 downto 0);
--	clkb: IN std_logic;
--	dia: IN std_logic_VECTOR(7 downto 0);
--	wea: IN std_logic;	 
--	rea: IN std_logic;
--	dob: OUT std_logic_VECTOR(7 downto 0));
--	end component blockdram;
	
	component sdh_frame_synchro_capture 
		port(
		 clk 				: in STD_LOGIC;
		 reset 				: in STD_LOGIC;
		 sdh_din 			: in STD_LOGIC_VECTOR(7 downto 0);
		 synchro_flag 		: out STD_LOGIC;
		 line_cnt_out 		: out STD_LOGIC_VECTOR(8 downto 0);
		 column_cnt_out 	: out STD_LOGIC_VECTOR(3 downto 0)
	     );
	end component sdh_frame_synchro_capture;
	
begin				   
	
	clk_divider : clk_proc
	port map(
			 clk_19m 		=> rc_clk,
			 reset 			=> reset,
			 clk_10m 		=> clk_10m,	
			 ena_64k		=> ena_64k,
			 ena_192k		=> ena_192k,
			 ena_1250k 		=> ena_1250k
		     );
	 
	sdh_fifo : blockdram
	generic map(36,8,6)
	port map(
			 addra		=> fifo_waddr,
			 clka		=> rc_clk,
		     addrb		=> fifo_raddr,
			 clkb		=> clk_10m,
			 dia		=> sdh_din,
			 wea		=> fifo_wren,	 
			 rea		=> fifo_rd_start,
			 dob		=> sdh_out_temp 
			 );    
			 
	sdh_frame_synchro : sdh_frame_synchro_capture
	port map(
			 clk 				=> rc_clk,
			 reset 				=> reset,
			 sdh_din 			=> sdh_din,
			 synchro_flag 		=> synchro_flag,
			 line_cnt_out 		=> line_cnt,
			 column_cnt_out 	=> column_cnt
		     );		   
			 
	fifo_wren <= '1' when synchro_flag='1' and column_cnt /= "0011" and (line_cnt <= "000001000") else
		         '0';	
			 
	process(reset,rc_clk)
	begin
		if reset='0' then
			fifo_waddr <= (others => '0');		  	
			ef_ena <= '0';
			ddc1_ena <= '0';	 
			E1_out <= '0';
			F1_out <= '0'; 		  
			index_ef <= 7;
			DDC1_out <= '0'; 		  
			index_ddc1 <= 23;
		elsif rc_clk'event and rc_clk='1' then	 
			clk_64k <= ena_64k_delay;
			clk_192k <= ena_192k_delay;
			ena_64k_delay <= ena_64k;
			ena_192k_delay <= ena_192k;
			e1_temp2 <= e1_temp1;
			e1_temp3 <= e1_temp2;
			if synchro_flag = '1' then			
				if column_cnt /= "0011" then
					if line_cnt <= "000001000" then	 
						if fifo_waddr /="100011" then
						fifo_waddr <= fifo_waddr + "00001";	
						else
							fifo_waddr <= "000000";
						end if;
					end if;			

					if column_cnt = "0001" then
						if line_cnt="000000011" then
							e1_temp1 <= sdh_din;
						elsif line_cnt="000000110" then
							f1_temp <= sdh_din;	   
							ef_ena <= '1'; 
						end if;
					elsif column_cnt = "0010" then
						if line_cnt="000000000" then
							ddc1_temp(23 downto 16) <= sdh_din;	 
							ddc1_ena <= '1';
						elsif line_cnt = "000000011" then
							ddc1_temp(15 downto 8) <= sdh_din; 
						elsif line_cnt = "000000110" then
							ddc1_temp(7 downto 0) <= sdh_din;
						end if;
					end if;
				end if;	 
				
				if ef_ena='1' then
					if ena_64k='1' then	  
						E1_out <= e1_temp3(index_ef);
						F1_out <= f1_temp(index_ef);
						if index_ef /=0 then
							index_ef <= index_ef-1;	
						else   
							index_ef <= 7;
						end if;
					end if;		
				end if;
				
				if ddc1_ena='1' then
					if ena_192k='1' then	  
						DDC1_out <= ddc1_temp(index_ddc1);
						if index_ddc1/=0 then
							index_ddc1 <= index_ddc1-1;	
						else   
							index_ddc1 <= 23;
						end if;
					end if;	
				end if;	 
			else	 
				index_ef <= 7;
				index_ddc1 <= 23;
				ef_ena <= '0';
				ddc1_ena <= '0';
			end if;	
		end if;	 		
	end process;  

	
	clk_10m_out <= clk_10m;
	process(reset, clk_10m)
	begin
		if reset='0' then	   
			sdh_cost_out <= '0';
			sdh_cost_den <= '0'; 
			fifo_raddr <= (others => '0');	   
			sdh_cost_cnt <= 0;		
			index_sdh<=7;	
			fifo_rd_start <= '0';
		elsif rising_edge(clk_10m) then	  		
			sdh_cost_den <= fifo_rd_start_delay;	
			fifo_rd_start_delay <= fifo_rd_start;
			ena_1250k_delay <= ena_1250k;
			if ena_1250k = '1' then
				if fifo_rd_start ='1' then
					if sdh_cost_cnt /= 71 then
						sdh_cost_cnt <= sdh_cost_cnt + 1;	  
						if fifo_raddr /= "100011" then
						fifo_raddr <= fifo_raddr + "00001";	
						else
							fifo_raddr<= "000000";  
						end if;
					else
						sdh_cost_cnt <= 0;	 
						fifo_rd_start <= '0';	
						fifo_raddr<= "000000";
					end if;	
				else
					if synchro_flag='1' and line_cnt >="001101111" and column_cnt="0100" then
						fifo_rd_start <= '1';
					end if;
				end if;		
			end if;	   
			
			if fifo_rd_start_delay = '1' then
				sdh_cost_out <= sdh_out_temp(index_sdh);
			end if;
			
			if ena_1250k_delay = '1' then
				index_sdh<=7;
			else
				index_sdh<= index_sdh-1;	
			end if;	
		end if;
	end process;
	


	 -- enter your statements here --

end sdh_transact_top;