alu.map.qmsg

实现16种运算的alu,包括+,-,+1,-1,与或非以及移位比较运算。经调试成功。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 17 10:22:54 2008 " "Info: Processing started: Thu Apr 17 10:22:54 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off alu -c alu " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off alu -c alu" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "alu.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file alu.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 alu-behav " "Info: Found design unit 1: alu-behav" {  } { { "alu.vhd" "" { Text "D:/alu/alu.vhd" 22 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 alu " "Info: Found entity 1: alu" {  } { { "alu.vhd" "" { Text "D:/alu/alu.vhd" 10 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "reg.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file reg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 reg-behav " "Info: Found design unit 1: reg-behav" {  } { { "reg.vhd" "" { Text "D:/alu/reg.vhd" 17 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 reg " "Info: Found entity 1: reg" {  } { { "reg.vhd" "" { Text "D:/alu/reg.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "alu " "Info: Elaborating entity \"alu\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "alu.vhd(84) " "Info: VHDL Case Statement information at alu.vhd(84): OTHERS choice is never selected" {  } { { "alu.vhd" "" { Text "D:/alu/alu.vhd" 84 0 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "271 " "Info: Implemented 271 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "24 " "Info: Implemented 24 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "18 " "Info: Implemented 18 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "229 " "Info: Implemented 229 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 17 10:23:00 2008 " "Info: Processing ended: Thu Apr 17 10:23:00 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0}  } {  } 0}