alu.fit.qmsg

实现16种运算的alu,包括+,-,+1,-1,与或非以及移位比较运算。经调试成功。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 17 10:23:03 2008 " "Info: Processing started: Thu Apr 17 10:23:03 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off alu -c alu " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off alu -c alu" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "alu EP1C6Q240C8 " "Info: Selected device EP1C6Q240C8 for design \"alu\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12Q240C8 " "Info: Device EP1C12Q240C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 29 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 29" {  } { { "alu.vhd" "" { Text "D:/alu/alu.vhd" 12 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "reset Global clock " "Info: Automatically promoted some destinations of signal \"reset\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "z1_tmp~27 " "Info: Destination \"z1_tmp~27\" may be non-global or may not use global clock" {  } { { "alu.vhd" "" { Text "D:/alu/alu.vhd" 25 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "A\[0\]~134 " "Info: Destination \"A\[0\]~134\" may be non-global or may not use global clock" {  } { { "alu.vhd" "" { Text "D:/alu/alu.vhd" 26 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "B\[0\]~109 " "Info: Destination \"B\[0\]~109\" may be non-global or may not use global clock" {  } { { "alu.vhd" "" { Text "D:/alu/alu.vhd" 26 -1 0 } }  } 0}  } { { "alu.vhd" "" { Text "D:/alu/alu.vhd" 12 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "reset " "Info: Pin \"reset\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "alu.vhd" "" { Text "D:/alu/alu.vhd" 12 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "reset" } } } } { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "" { reset } "NODE_NAME" } "" } } { "D:/alu/alu.fld" "" { Floorplan "D:/alu/alu.fld" "" "" { reset } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "7.934 ns register register " "Info: Estimated most critical path is register to register delay of 7.934 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns B\[0\] 1 REG LAB_X10_Y15 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X10_Y15; Fanout = 6; REG Node = 'B\[0\]'" {  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "" { B[0] } "NODE_NAME" } "" } } { "alu.vhd" "" { Text "D:/alu/alu.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.696 ns) + CELL(0.590 ns) 1.286 ns add~1666 2 COMB LAB_X9_Y15 2 " "Info: 2: + IC(0.696 ns) + CELL(0.590 ns) = 1.286 ns; Loc. = LAB_X9_Y15; Fanout = 2; COMB Node = 'add~1666'" {  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "1.286 ns" { B[0] add~1666 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.256 ns) + CELL(0.442 ns) 2.984 ns add~1677 3 COMB LAB_X11_Y14 1 " "Info: 3: + IC(1.256 ns) + CELL(0.442 ns) = 2.984 ns; Loc. = LAB_X11_Y14; Fanout = 1; COMB Node = 'add~1677'" {  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "1.698 ns" { add~1666 add~1677 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.222 ns) + CELL(0.442 ns) 3.648 ns Mux~3077 4 COMB LAB_X11_Y14 2 " "Info: 4: + IC(0.222 ns) + CELL(0.442 ns) = 3.648 ns; Loc. = LAB_X11_Y14; Fanout = 2; COMB Node = 'Mux~3077'" {  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "0.664 ns" { add~1677 Mux~3077 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.313 ns) + CELL(0.442 ns) 5.403 ns Mux~3177 5 COMB LAB_X8_Y15 1 " "Info: 5: + IC(1.313 ns) + CELL(0.442 ns) = 5.403 ns; Loc. = LAB_X8_Y15; Fanout = 1; COMB Node = 'Mux~3177'" {  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "1.755 ns" { Mux~3077 Mux~3177 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.260 ns) + CELL(0.442 ns) 7.105 ns Mux~3178 6 COMB LAB_X11_Y14 1 " "Info: 6: + IC(1.260 ns) + CELL(0.442 ns) = 7.105 ns; Loc. = LAB_X11_Y14; Fanout = 1; COMB Node = 'Mux~3178'" {  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "1.702 ns" { Mux~3177 Mux~3178 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.222 ns) + CELL(0.607 ns) 7.934 ns result_t\[0\] 7 REG LAB_X11_Y14 2 " "Info: 7: + IC(0.222 ns) + CELL(0.607 ns) = 7.934 ns; Loc. = LAB_X11_Y14; Fanout = 2; REG Node = 'result_t\[0\]'" {  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "0.829 ns" { Mux~3178 result_t[0] } "NODE_NAME" } "" } } { "alu.vhd" "" { Text "D:/alu/alu.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.965 ns 37.37 % " "Info: Total cell delay = 2.965 ns ( 37.37 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.969 ns 62.63 % " "Info: Total interconnect delay = 4.969 ns ( 62.63 % )" {  } {  } 0}  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "7.934 ns" { B[0] add~1666 add~1677 Mux~3077 Mux~3177 Mux~3178 result_t[0] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 8 " "Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 8%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 17 10:23:08 2008 " "Info: Processing ended: Thu Apr 17 10:23:08 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0}  } {  } 0}